CY7C344

ALL NEW DESIGNS

Document #: 38-03006 Rev. *B

Page 7 of 15

7C344-15

7C344-20

7C344-25

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Dedicated Input Pad and Buffer Delay

Com’l/Ind

4

5

7

ns

Mil

4

5

7

I/O Input Pad and Buffer Delay

Com’l/Ind

4

5

7

ns

Mil

4

5

7

Expander Array Delay

Com’l/Ind

8

10

15

ns

Mil

8

10

15

Logic Array Data Delay

Com’l/Ind

7

9

10

ns

Mil

7

9

10

Logic Array Control Delay

Com’l/Ind

5

7

7

ns

Mil

5

7

7

Output Buffer and Pad Delay

Com’l/Ind

4

5

5

ns

Mil

4

5

5

Output Buffer Enable Delay[27]

Com’l/Ind

7

8

11

ns

Mil

7

8

11

Output Buffer Disable Delay

Com’l/Ind

7

8

11

ns

Mil

7

8

11

Register Set-Up Time Relative to Clock Signal

at Register

Com’l/Ind

5

5

8

ns

Mil

5

5

8

Register Hold Time Relative to Clock Signal at

Register

Com’l/Ind

7

9

12

ns

Mil

7

9

12

Flow-Through Latch Delay

Com’l/Ind

1

1

3

ns

Mil

1

1

3

Register Delay

Com’l/Ind

1

1

1

ns

Mil

1

1

1

Transparent Mode Delay[28]

Com’l/Ind

1

1

3

ns

Mil

1

1

3

Clock HIGH Time

Com’l/Ind

6

7

8

ns

Mil

6

7

8

Clock LOW Time

Com’l/Ind

6

7

8

ns

Mil

6

7

8

Asynchronous Clock Logic Delay

Com’l/Ind

7

8

10

ns

Mil

7

8

10

Synchronous Clock Delay

Com’l/Ind

1

2

3

ns

Mil

1

2

3

Feedback Delay

Com’l/Ind

1

1

1

ns

Mil

1

1

1

Asynchronous Register Preset Time

Com’l/Ind

5

6

9

ns

Mil

5

6

9

Notes:

27. Sample tested only for an output change of 500 mV.

28. This specification guarantees the maximum combinatorial delay associated with the macrocell register bypass when the macrocell is configured for combinatorial

operation.