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CYRF89235 Folha de dados(PDF) 21 Page - Cypress Semiconductor |
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CYRF89235 Folha de dados(HTML) 21 Page - Cypress Semiconductor |
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21 / 45 page ![]() CYRF89235 Document Number: 001-77748 Rev. *F Page 21 of 45 DC GPIO Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 2.4 V to 3.0 V and 0 °C TA 70 °C, or 1.9 V to 2.4 V and 0 °C TA °C, respectively. Typical parameters apply to 3.3 V at 25 °C and are for design guidance only. Table 13. 2.4 V to 3.0 V DC GPIO Specifications Symbol Description Conditions Min Typ Max Units RPU Pull-up resistor – 4 5.60 8 k VOH1 High output voltage Port 2 or 3 or 4 pins IOH < 10 A, maximum of 10 mA source current in all I/Os VIN – 0.20 – – V VOH2 High output voltage Port 2 or 3 or 4 pins IOH = 0.2 mA, maximum of 10 mA source current in all I/Os VIN – 0.40 – – V VOH3 High output voltage Port 0 or 1 pins with LDO regulator Disabled for port 1 IOH < 10 A, maximum of 10 mA source current in all I/Os VIN – 0.20 – – V VOH4 High output voltage Port 0 or 1 pins with LDO regulator Disabled for Port 1 IOH = 2 mA, maximum of 10 mA source current in all I/Os VIN – 0.50 – – V VOH5A High output voltage Port 1 pins with LDO enabled for 1.8 V out IOH < 10 A, VIN > 2.4 V, maximum of 20 mA source current in all I/Os 1.50 1.80 2.10 V VOH6A High output voltage Port 1 pins with LDO enabled for 1.8 V out IOH = 1 mA, VIN > 2.4 V, maximum of 20 mA source current in all I/Os 1.20 – – V VOL Low output voltage IOL = 10 mA, maximum of 30 mA sink current on even port pins (for example, P0[2] and P1[4]) and 30 mA sink current on odd port pins (for example, P0[3] and P1[5]) – – 0.75 V VIL Input low voltage – – – 0.72 V VIH Input high voltage – 1.40 – V VH Input hysteresis voltage – – 80 – mV IIL Input leakage (absolute value) – – 1 1000 nA CPIN Capacitive load on pins Package and pin dependent Temp = 25 C 0.50 1.70 7 pF VILLVT2.5 Input Low Voltage with low threshold enable set, Enable for Port1 Bit3 of IO_CFG1 set to enable low threshold voltage of Port1 input 0.7 V – VIHLVT2.5 Input High Voltage with low threshold enable set, Enable for Port1 Bit3 of IO_CFG1 set to enable low threshold voltage of Port1 input 1.2 – V |
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