Z8018010VSC datasheet(49/85 Pages) ZILOG

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Z80180

Microprocessor Unit

PS014004-1106

Architecture

ASCI Channel Control Register B

Figure 33. ASCI Channel Control Register B

MPBT: Multiprocessor Bit Transmit (bit 7)—

When multiprocessor communication format

is selected (MP bit = 1), MPBT is used to specify the MPB data bit for transmission. If MPBT

= 1

, then MPB = 1 is transmitted. If MPBT = 0, then MPB = 0 is transmitted. MPBT state is

undefined during and after RESET.

MP: Multiprocessor Mode (bit 6)—

When MP is set to 1, the data format is configured for

multiprocessor mode based on the MOD2 (number of data bits) and MOD0 (number of stop

bits) bits in CNTLA. The format is as follows.

Start bit + 7 or 8 data bits + MPB bit + 1 or 2 stop bits

Multiprocessor (MP=1) format does not feature any provision for parity.

If MP = 0, the data format is based on MOD0, MOD1, MOD2, and may include parity. The MP

bit is cleared to 0 during RESET.

CTS/PS: Clear to Send/Prescale (bit 5)—If bit 5 of the System Configuration Register

is 0, the CTS0/RxS pin features the CTS0 function, and the state of the pin can be read in bit 5

Table 11. Data Formats

MOD2

MOD1

MOD0

Data Format

Start + 7 bit data + 1 stop

Start + 7 bit data + 2 stop

Start + 7 bit data + parity + 1 stop

Start + 7 bit data + parity + 2 stop

Start + 8 bit data + 1 stop

Start + 8 bit data + 2 stop

Start + 8 bit data + parity + 1 stop

Start + 8 bit data + parity + 2 stop

ASCI Channel Control Register B

Bit

MPBT

R/W

CTS/

PEO

SS2

SS1

SS0

R/W

ASCI Control Register B 1 (CNTLB1: I/O Address = 03h)

R/W

ASCI Control Register B 0 (CNTLB0: I/O Address = 02h)

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