AD5302ARM datasheet(5/24 Pages) AD

Nome de Peças	AD5302ARM

Descrição Electrónicos	2.5 V to 5.5 V, 230 關A, Dual Rail-to-Rail, Voltage Output 8-/10-/12-Bit DACs

PDF	24 Pages

Scroll/Zoom	100%

Fabricante Electrônico	AD [Analog Devices]

Página de início	http://www.analog.com

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5 / 24 page

AD5302/AD5312/AD5322

Rev. D | Page 5 of 24

TIMING CHARACTERISTICS

VDD = 2.5 V to 5.5 V, all specifications TMIN to TMAX, unless otherwise noted.1, 2, 3

Table 3.

Parameter

Limit at TMIN, TMAX (A, B Version)

Unit

Conditions/Comments

ns min

SCLK Cycle Time

ns min

SCLK High Time

ns min

SCLK Low Time

ns min

SYNC to SCLK Active Edge Setup Time

ns min

Data Setup Time

4.5

ns min

Data Hold Time

ns min

SCLK Falling Edge to SYNC Rising Edge

100

ns min

Minimum SYNC High Time

ns min

LDAC Pulse Width

t10

ns min

SCLK Falling Edge to LDAC Rising Edge

1 Guaranteed by design and characterization, not production tested.

2 All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

3 See Figure 2.

SCLK

DIN1

DB15

DB0

1SEE INPUT SHIFT REGISTER SECTION.

t10

LDAC

SYNC

Figure 2. Serial Interface Timing Diagram

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