PIC16F753 datasheet(23/238 Pages) MICROCHIP

23 / 238 page

 2013 Microchip Technology Inc.

Preliminary

DS40001709A-page 23

PIC16F753/HV753

2.3.7

PIR2 REGISTER

The PIR2 register contains the Peripheral Interrupt flag

bits, as shown in Register 2-7.

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Enable bit, GIE of the INTCON register.

User

software

should

ensure

the

appropriate interrupt flag bits are clear prior

to enabling an interrupt.

PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 1

U-0

R/W-0

U-0

R/W-0

U-0

R/W-0

—

C2IF

C1IF

—COG1IF

—

CCP1IF

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-6

Unimplemented: Read as ‘0’

bit 5

C2IF: Comparator 1 Interrupt Flag bit

1 = Comparator output (C2OUT bit) has changed (must be cleared in software)

0 = Comparator output (C2OUT bit) has not changed

bit 4

C1IF: Comparator 1 Interrupt Flag bit

1 = Comparator output (C1OUT bit) has changed (must be cleared in software)

0 = Comparator output (C1OUT bit) has not changed

bit 3

Unimplemented: Read as ‘0’

bit 2

COG1IF: COG 1 Interrupt Flag bit

1 = COG1 has generated an auto-shutdown interrupt

0 = COG1 has NOT generated an auto-shutdown interrupt

bit 1

Unimplemented: Read as ‘0’

bit 0

CCP1IF: ECCP Interrupt Flag bit

Capture Mode

1 = A TMR1 register capture occurred (must be cleared in software)

0 = No TMR1 register capture occurred

Compare Mode

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

PWM mode

Unused in this mode

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