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OR3LP26B Folha de dados(PDF) 52 Page - Agere Systems

Nome de Peças OR3LP26B
Descrição Electrónicos  Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
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ORCA OR3LP26B FPSC
Data Sheet
Embedded Master/Target PCI Interface
March 2000
52
Lucent Technologies Inc.
Lucent Technologies Inc.
PCI Bus Core Detailed Description Dual Port (continued)
Target Write to Configuration Space Transaction
Figure 10 shows the timing on the PCI interface for a Target write to configuration space. Accesses of configuration
space occur without any involvement of the FPGA interface. All configuration space accesses are disconnected
with data on the first data word and are thus restricted from bursting. Address decode speed is medium, and the
PCI core signals that it is ready to receive the data by asserting trdyn one cycle after devseln is asserted.
5-8851(F).a
Figure 10. Target Configuration Write (PCI Bus, 64-Bit)
T0
T1
T2
T3
T4
T5
T6
X
ADDRESS
DATA
X
X
CMD
BYTE ENABLES
X
X
X
clk
framen
ad
c_ben
idsel
irdyn
devseln
trdyn
stopn



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