Advance Data Sheet

March 2000

4

Features

Hex 10 Mbits/s Transceiver

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DSP based.

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Compatible with

for twisted-pair cable.

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Half- and full-duplex operations.

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Autopolarity detection and correction.

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Adjustable squelch level for extended wire-length

capability (two levels).

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Interfaces with

interface (MII) or a serial 10 Mbits/s 7-pin interface.

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On-chip filtering eliminates the need for external fil-

ters.

Hex 100 Mbits/s Transceiver

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Compatible with

PCS/PMA (clause 24), PMD (clause 25), MII man-

agement, and autonegotiation (clause 28) specifi-

cations.

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Selectable 5-bit code-group (PDT/PDR interface)

or 4-bit data nibbles (MII interface) input/output.

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Full- or half-duplex operations.

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Optional carrier integrity monitor (CIM).

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Selectable carrier sense signal generation (MCRS)

asserted during either transmission or reception in

half duplex (MCRS asserted during reception only

in full duplex).

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Adaptive equalization and baseline wander correc-

tion.

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On-chip filtering eliminates the need for external

filters.

*

Electronics Engineers, Inc.

Hex 100 Mbits/s FX Transceiver

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Compatible with

dard.

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Reuses existing twisted-pair I/O pins for compatible

fiber-optic transceiver pseudo-ECL (PECL) data.

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Fiber mode automatically configures port:

— FX mode enable is pin or register selectable

— Disables autonegotiation and 10Base-T.

— Enables 100Base-FX remote fault signaling.

— Disables MLT-3 encoder/decoder.

— Disables scrambler/descrambler.

General

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Ports individually configurable

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Autonegotiation and management:

— Fast link pulse (FLP) burst generator.

— Arbitration function.

— Accepts preamble suppression.

— Operates up to 12.5 MHz.

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Supports the MII station management protocol and

frame format (clause 22): basic and extended reg-

ister set.

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Supports next page.

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Provides status signals: receive activity, transmit

activity, full duplex, collision/jabber, link integrity,

and speed indication.

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Powerdown mode for 10 Mbits/s and 100 Mbits/s

operation.

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Loopback testing for 10 Mbits/s and 100 Mbits/s

operation.

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0.25

µm low-power CMOS technology.

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Single 3.3 V power supply operation.

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25 MHz XTAL oscillator input or 25 MHz/50 MHz/

125 MHz clock input.

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Compatible with RMII (standard version) and SMII

(standard version).

Note: Advisories are issued as needed to update product information. When using this data sheet for design purposes, please contact

your Lucent Technologies Microelectronics Group Account Manager to obtain the latest advisory on this product.

DNC3X3625

Hex 10/100 Mbits/s Ethernet Transceiver Macrocell