SN65DSI85 datasheet(21/45 Pages) TI

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SN65DSI85

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SLLSEB9C – SEPTEMBER 2012 – REVISED DECEMBER 2012

ULPS

The SN65DSI85 supports the MIPI® defined ultra-low power state (ULPS). While the device is in the ULPS, the

CSR registers are accessible via I2C interface. ULPS sequence should be issued to all active DSI CLK and/or

DSI data lanes of the enabled DSI Channels for the SN65DSI85 enter the ULPS. The Following sequence should

be followed to enter and exit the ULPS.

1. Host issues a ULPS entry sequence to all DSI CLK and data lanes enabled.

2. When host is ready to exit the ULPS mode, host issues a ULPS exit sequence to all DSI CLK and data lanes

that need to be active in normal operation.

3. Wait for the PLL_LOCK bit (CSR 0x0A.7) to be set.

4. Set the SOFT_RESET bit (CSR 0x09.0).

5. Device resumes normal operation.(i.e video streaming resumes on the panel).

LVDS Pattern Generation

The SN65DSI85 supports a pattern generation feature on LVDS Channels. This feature can be used to test the

LVDS output path and LVDS panels in a system platform. The pattern generation feature can be enabled by

setting the CHA_TEST_PATTERN bit at address 0x3C. No DSI data is received while the pattern generation

feature is enabled.

There are three modes available for LVDS test pattern generation. The mode of test pattern generation is

determined by register configuration as shown in the tables below.

Table 2. Test Pattern Generation

Test pattern generation mode

LVDS_LINK_CFG(CSR 0x18.4) = 1b

DSI_CH_MODE(CSR 0x10.6:5) = XXb

Single LVDS configuration mode

CHA_TEST_PATTERN(CSR 0x3C.4) = 1b

CHB_TEST_PATTERN(CSR 0x3C.0) = 0b

LVDS_LINK_CFG(CSR 0x18.4) = 0b

DSI_CH_MODE(CSR 0x10.6:5) = 0Xb

Dual LVDS configuration mode

CHA_TEST_PATTERN(CSR 0x3C.4) = 1b

CHB_TEST_PATTERN(CSR 0x3C.0) = 0b

LVDS_LINK_CFG(CSR 0x18.4) = 0b

Two independent LVDS configuration

DSI_CH_MODE(CSR 0x10.6:5) = 10b

mode

CHA_TEST_PATTERN(CSR 0x3C.4) = 1b

CHB_TEST_PATTERN(CSR 0x3C.0) = 1b

The following tables shows a list of video registers that need to be configured for test pattern generation video

parameters.

1. Single LVDS configuration

Table 3. Video Registers

Addr. bit

0x20.7:0

CHA_ACTIVE_LINE_LENGTH_LOW

0x21.3:0

CHA_ACTIVE_LINE_LENGTH_HIGH

0x24.7:0

CHA_VERTICAL_DISPLAY_SIZE_LOW

0x25.3:0

CHA_VERTICAL_DISPLAY_SIZE_HIGH

0x2C.7:0

CHA_HSYNC_PULSE_WIDTH_LOW

0x2D.1:0

CHA_HSYNC_PULSE_WIDTH_HIGH

0x30.7:0

CHA_VSYNC_PULSE_WIDTH_LOW

0x31.1:0

CHA_VSYNC_PULSE_WIDTH_HIGH

0x34.7:0

CHA_HORIZONTAL_BACK_PORCH

0x36.7:0

CHA_VERTICAL_BACK_PORCH

0x38.7:0

CHA_HORIZONTAL_FRONT_PORCH

0x3A.7:0

CHA_VERTICAL_FRONT_PORCH

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