CMP401/ CMP402

REV. 0

–4–

WARNING!

ESD SENSITIVE DEVICE

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the CMP401/CMP402 features proprietary ESD protection circuitry, permanent damage

may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

ABSOLUTE MAXIMUM RATINGS

1

Total Analog Supply Voltage . . . . . . . . . . . . . . . . . . . . . +16 V

Digital Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V

Analog Positive Supply—Digital Positive Supply . . . . –200 mV

Input Voltage

2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±7 V

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . .

±9 V

Output Short-Circuit Duration to GND . . . . . . . . . Indefinite

Storage Temperature Range

P, S, RU Package . . . . . . . . . . . . . . . . . . . –65

°C to +150°C

Operating Temperature Range

CMP401G, CMP402G . . . . . . . . . . . . . . –40

°C to +125°C

Junction Temperature Range

P, S, RU Package . . . . . . . . . . . . . . . . . . . –65

°C to +150°C

Lead Temperature Range (Soldering, 60 sec) . . . . . . . +300

°C

Package Type

JA

3

JC

Units

16-Pin Plastic DIP (P)

90

47

°C/W

16-Pin SO (S)

113

37

°C/W

16-Lead TSSOP (RU)

180

37

°C/W

NOTES

otherwise noted.

± 7 volts or the analog supply voltage,

whichever is less.

3

θ

θ

for P-DIP, and

θ

TSSOP packages.

ORDERING GUIDE

Temperature

Package

Package

Model

Range

Description

Option

CMP401GP

–40

°C to +125°C 16-Pin Plastic DIP N-16

CMP401GS

–40

°C to +125°C 16-Pin SOIC

R-16A

CMP401GRU

–40

°C to +125°C 16-Lead TSSOP

RU-16

CMP402GP

–40

°C to +125°C 16-Pin Plastic DIP N-16

CMP402GS

–40

°C to +125°C 16-Pin SOIC

R-16A

CMP402GRU

–40

°C to +125°C 16-Lead TSSOP

RU-16

DICE CHARACTERISTICS

2

1

16 15

89

3

4

5

6

7

14

13

12

11

10

CMP401/CMP402 Die Size 0.065

× 0.069 inch, 4,485 sq. mils

Substrate (Die Backside) Is Connected to V+

Transistor Count 104.

+IN

–IN

V+ ANA

V– ANA

V+ DIG

OUT

DIG GND

Figure 1. Simplified Schematic

CMP401/CMP402 PIN CONFIGURATIONS

16-Lead Epoxy DIP

(P Suffix)

16-Lead Narrow-SO

(S Suffix)

16-Lead

TSSOP

(RU Suffix)

OUT B

OUT A

V+ DIG

V+ ANA

–IN A

+IN A

–IN B

+IN B

V– ANA

DIG GND

OUT D

OUT C

–IN C

+IN D

–IN D

+IN C

116

8

9

TOP VIEW

(Not to Scale)

CMP401/

402

14

13

12

11

16

15

10

9

8

1

2

3

4

7

6

5

OUT B

OUT A

V+ DIG

V+ ANA

–IN A

+IN A

–IN B

+IN B

V– ANA

DIG GND

OUT D

OUT C

–IN C

+IN D

–IN D

+IN C

TOP VIEW

(Not to Scale)

CMP401/

402

14

13

12

11

16

15

10

9

8

1

2

3

4

7

6

5

OUT B

OUT A

V+ DIG

V+ ANA

–IN A

+IN A

–IN B

+IN B

V– ANA

DIG GND

OUT D

OUT C

–IN C

+IN D

–IN D

+IN C