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AD9845A Folha de dados(PDF) 12 Page - Analog Devices

Nome de Peças AD9845A
Descrição Electrónicos  Complete 12-Bit 30 MSPS CCD Signal Processor
PDF  22 Pages
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
Logo AD - Analog Devices

AD9845A Folha de dados(HTML) 12 Page - Analog Devices

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REV. 0
AD9845A
–12–
0101...
0101...
0101...
NOTE: 0 = GAIN0, 1 = GAIN1, 2 = GAIN2, 3 = GAIN3
2323...
2323...
2323...
HD
LINE 0
LINE 1
LINE 2
LINE m
LINE m–1
LINE 0
LINE 1
LINE 2
LINE m
LINE m–1
EVEN FIELD
ODD FIELD
VD
Figure 16. PxGA Mode 5 (VD Selected) Frame/Line Gain Register Sequence
SHP
HD
5 PIXEL MIN
PxGA GAIN
GAIN0
GAIN1
GAIN0
NOTES:
1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES.
2. EVERY HD RISING EDGE WITH A PREVIOUS VD FALLING EDGE WILL RESET TO 0101.
3. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 2323.
4. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL REPEAT EITHER 0101... (EVEN) OR 2323 ... (ODD).
GAIN3
GAIN2
GAINX
GAINX
3ns MIN
VD
3ns MIN
Figure 17. PxGA Mode 5 (VD Selected) Detailed Timing
FRAME n
VD
HD
LINE 0
LINE 1
LINE 2
LINE m
0101...
1212...
0101...
LINE m–1
LINE 0
LINE 1
LINE 2
LINE m
0101...
1212...
0101...
LINE m–1
NOTE: 0 = GAIN0, 1 = GAIN1, 2 = GAIN2
FRAME n+1
Figure 18. PxGA Mode 6 (Mosaic Repeat) Frame/Line Gain Register Sequence
SHP
HD
PxGA GAIN
GAIN0
GAIN1
GAIN0
NOTES:
1. MINIMUM PULSEWIDTH FOR HD AND VD IS 5 PIXEL CYCLES.
2. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES. MINIMUM SET-UP TIME IS 3ns.
3. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 0101.
4. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL ALTERNATE BETWEEN 0101... AND 1212.
GAIN2
GAINX
GAINX
GAIN1
3ns MIN
VD
3ns MIN
5 PIXEL MIN
Figure 19. PxGA Mode 6 (Mosaic Repeat) Detailed Timing



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