AD9830AST datasheet(3/16 Pages) AD

3 / 16 page

AD9830

REV. A

–3–

TIMING CHARACTERISTICS

Limit at

TMIN to TMAX

Parameter

(A Version)

Units

Test Conditions/Comments

ns min

MCLK Period

ns min

MCLK High Duration

ns min

MCLK Low Duration

ns min

Rising Edge Before MCLK Rising Edge

t4A

ns min

Rising Edge After MCLK Rising Edge

ns min

Pulse Width

ns min

Duration Between Consecutive WR Pulses

ns min

Data/Address Setup Time

ns min

Data/Address Hold Time

ns min

FSELECT, PSEL0, PSEL1 Setup Time Before MCLK Rising Edge

t9A

ns min

FSELECT, PSEL0, PSEL1 Setup Time After MCLK Rising Edge

t10

ns min

RESET

Pulse Duration

NOTES

1See Pin Description section.

Guaranteed by design, but not production tested.

t4A

MCLK

Figure 2. WR–MCLK Relationship

A0, A1, A2

DATA

VALID DATA

Figure 3. Writing to a Phase/Frequency Register

VALID DATA

t9A

t10

MCLK

FSELECT

PSEL0, PSEL1

RESET

Figure 4. Control Timing

(VDD = +5 V

5%; AGND = DGND = 0 V, unless otherwise noted)

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