AD9775EB datasheet(7/48 Pages) AD

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REV. 0

AD9775

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PIN FUNCTION DESCRIPTIONS

Pin Number

Mnemonic

Description

1, 3

CLKVDD

Clock Supply Voltage

LPF

PLL Loop Filter

4, 7

CLKGND

Clock Supply Common

CLK+

Differential Clock Input

CLK–

Differential Clock Input

DATACLK/PLL_LOCK

With the PLL enabled, this pin indicates the state of the PLL. A read of a

Logic “1” indicates the PLL is in the locked state. Logic “0” indicates the

PLL has not achieved lock. This pin may also be programmed to act as

either an input or output (Address 02h, Bit 3) DATACLK signal running at

the input data rate.

9, 17, 25, 35, 44, 52

DGND

Digital Common

10, 18, 26, 36, 43, 51

DVDD

Digital Supply Voltage

11–16, 19–24, 27, 28

P1B13 (MSB) to P1B0 (LSB) Port “1” Data Inputs

29, 30, 49, 50

No Connect

IQSEL/P2B13 (MSB)

In “1” port mode, IQSEL = 1 followed by a rising edge of the differential

input clock will latch the data into the I channel input register. IQSEL = 0

will latch the data into the Q channel input register. In “2” port mode, this

pin becomes the port “2” MSB.

ONEPORTCLK/P2B12

With the PLL disabled and the AD9775 in “1” port mode, this pin becomes

a clock output that runs at twice the input data rate of the I and Q channels.

This allows the AD9775 to accept and demux interleaved I and Q data to

the I and Q input registers.

33, 34, 37–42, 45–48

P2B11 to P2B0 (LSB)

Port “2” Data Inputs

SPI_SDO

In the case where SDIO is an input, SDO acts as an output. When SDIO

becomes an output, SDO enters a High-Z state.

SPI_SDIO

Bidirectional Data Pin. Data direction is controlled by Bit 7 of Register

Address 00h. The default setting for this bit is “0,” which sets SDIO as an input.

SPI_CLK

Data input to the SPI port is registered on the rising edge of SPI_CLK.

Data output on the SPI port is registered on the falling edge.

SPI_CSB

Chip Select/SPI Data Synchronization. On momentary logic high, resets

SPI port logic and initializes instruction cycle.

RESET

Logic “1” resets all of the SPI port registers, including Address 00h, to their

default values. A software reset can also be done by writing a Logic “1” to

SPI Register 00h, Bit 5. However, the software reset has no effect on the bits

in Address 00h.

REFIO

Reference Output, 1.2 V Nominal

FSADJ2

Full-Scale Current Adjust, Q Channel

FSADJ1

Full-Scale Current Adjust, I Channel

61, 63, 65, 76, 78, 80

AVDD

Analog Supply Voltage

62, 64, 66, 67, 70, 71, AGND

Analog Common

74, 75, 77, 79

68, 69

IOUTA2, IOUTB2

Differential DAC Current Outputs, Q Channel

72, 73

IOUTA1, IOUTB1

Differential DAC Current Outputs, I Channel

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