AD9762 datasheet(14/23 Pages) AD

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AD9762

–14–

REV. B

IOUTA and IOUTB also have a negative and positive voltage

compliance range that must be adhered to in order to achieve

optimum performance. The negative output compliance range

of –1.0 V is set by the breakdown limits of the CMOS process.

Operation beyond this maximum limit may result in a break-

down of the output stage and affect the reliability of the AD9762.

The positive output compliance range is slightly dependent

on the full-scale output current, IOUTFS. It degrades slightly

from its nominal 1.25 V for an IOUTFS = 20 mA to 1.00 V for an

IOUTFS = 2 mA. The optimum distortion performance for a

single-ended or differential output is achieved when the maximum

full-scale signal at IOUTA and IOUTB does not exceed 0.5 V.

Applications requiring the AD9762’s output (i.e., VOUTA and/

or VOUTB) to extend its output compliance range should size

RLOAD accordingly. Operation beyond this compliance range

will adversely affect the AD9762’s linearity performance and

subsequently degrade its distortion performance.

DIGITAL INPUTS

The AD9762’s digital input consists of 12 data input pins and a

clock input pin. The 12-bit parallel data inputs follow standard

positive binary coding where DB11 is the most significant bit

(MSB) and DB0 is the least significant bit (LSB). IOUTA produces

a full-scale output current when all data bits are at Logic 1.

IOUTB produces a complementary output with the full-scale current

split between the two outputs as a function of the input code.

The digital interface is implemented using an edge-triggered

master slave latch. The DAC output is updated following the

rising edge of the clock as shown in Figure 1 and is designed

to support a clock rate as high as 125 MSPS. The clock can

be operated at any duty cycle that meets the specified latch

pulsewidth. The set-up and hold times can also be varied within

the clock cycle as long as the specified minimum times are met;

although the location of these transition edges may affect digital

feedthrough and distortion performance. Best performance is

typically achieved when the input data transitions on the falling edge

of a 50% duty cycle clock.

The digital inputs are CMOS compatible with logic thresholds,

VTHRESHOLD set to approximately half the digital positive supply

(DVDD) or

VTHRESHOLD = DVDD/2 (

±20%)

The internal digital circuitry of the AD9762 is capable of operating

over a digital supply range of 2.7 V to 5.5 V. As a result, the

digital inputs can also accommodate TTL levels when DVDD is

set to accommodate the maximum high level voltage of the TTL

drivers VOH(MAX). A DVDD of 3 V to 3.3 V will typically ensure

proper compatibility with most TTL logic families. Figure 46

shows the equivalent digital input circuit for the data and clock

inputs. The sleep mode input is similar with the exception that

it contains an active pull-down circuit, thus ensuring that the

AD9762 remains enabled if this input is left disconnected.

DVDD

DIGITAL

INPUT

Figure 46. Equivalent Digital Input

Since the AD9762 is capable of being updated up to 125 MSPS,

the quality of the clock and data input signals are important

in achieving the optimum performance. The drivers of the

digital data interface circuitry should be specified to meet the

minimum set-up and hold times of the AD9762 as well as its

required min/max input logic level thresholds. Typically, the

selection of the slowest logic family that satisfies the above

conditions will result in the lowest data feedthrough and noise.

Digital signal paths should be kept short and run lengths

matched to avoid propagation delay mismatch. The insertion of

a low value resistor network (i.e., 20

Ω to 100 Ω) between the

AD9762 digital inputs and driver outputs may be helpful in

reducing any overshooting and ringing at the digital inputs that

contribute to data feedthrough. For longer run lengths and high

data update rates, strip line techniques with proper termination

resistors should be considered to maintain “clean” digital

inputs. Also, operating the AD9762 with reduced logic swings

and a corresponding digital supply (DVDD) will also reduce

data feedthrough.

The external clock driver circuitry should provide the AD9762

with a low jitter clock input meeting the min/max logic levels

while providing fast edges. Fast clock edges will help minimize

any jitter that will manifest itself as phase noise on a recon-

structed waveform. Thus, the clock input should be driven by

the fastest logic family suitable for the application.

Note, the clock input could also be driven via a sine wave,

which is centered around the digital threshold (i.e., DVDD/2),

and meets the min/max logic threshold. This will typically result

in a slight degradation in the phase noise, which becomes more

noticeable at higher sampling rates and output frequencies.

Also, at higher sampling rates, the 20% tolerance of the digital

logic threshold should be considered since it will affect the

effective clock duty cycle and subsequently cut into the required

data set-up and hold times.

SLEEP MODE OPERATION

The AD9762 has a power-down function which turns off the

output current and reduces the supply current to less than

8.5 mA over the specified supply range of 2.7 V to 5.5 V and

temperature range. This mode can be activated by applying

a logic level “1” to the SLEEP pin. This digital input also

contains an active pull-down circuit that ensures the AD9762

remains enabled if this input is left disconnected. The SLEEP

input with active pull-down requires <40

µA of drive current.

The power-up and power-down characteristics of the AD9762

are dependent upon the value of the compensation capacitor

connected to COMP1. With a nominal value of 0.1

µF, the

AD9762 takes less than 5

µs to power down and approximately

3.25 ms to power back up. Note, the SLEEP MODE should not

be used when the external control amplifier is used as shown in

Figure 45.

POWER DISSIPATION

The power dissipation, PD, of the AD9762 is dependent on

several factors which include: (1) AVDD and DVDD, the power

supply voltages; (2) IOUTFS, the full-scale current output; (3)

fCLOCK, the update rate; (4) and the reconstructed digital input

waveform. The power dissipation is directly proportional to the

analog supply current, IAVDD, and the digital supply current, IDVDD.

IAVDD is directly proportional to IOUTFS as shown in Figure 47

and is insensitive to fCLOCK.

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