AD9731 datasheet(3/11 Pages) AD

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–3–

REV. A

AD9731

5/27/99 8 PM

Parameter

Temp

Test Level

Min

Typ

Max

Units

SFDR PERFORMANCE (Narrowband)

2 MHz; 2 MHz Span

+25

°CV

25 MHz, 2 MHz Span

+25

°CV

10 MHz, 5 MHz Span (Clock = 170 MHz)

+25

°CV

INTERMODULATION DISTORTION

F1 = 800 kHz, F2 = 900 kHz

+25

°CV

POWER SUPPLY

Digital –V Supply Current

+25

°C

Full

Analog –V Supply Current

+25

°C

Full

Digital +V Supply Current

+25

°C

Full

Power Dissipation

+25

°C

439

Full

449

PSRR

+25

°C

100

µA/V

NOTES

1Measured as an error in ratio of full-scale current to current through R

SET (640 µA nominal); ratio is nominally 32. DAC load is virtual ground.

2Internal reference voltage is tested under load conditions specified in Internal Reference Output current specification.

3Internal reference output current defines load conditions applied during Internal Reference Voltage test.

4Full-scale current variations among devices are higher when driving REFERENCE IN directly.

5Frequency at which a 3 dB change in output of DAC is observed; R

L = 50 Ω; 100 mV modulation at midscale.

6Based on I

FS = 32 (CONTROL AMP IN/RSET) when using internal control amplifier. DAC load is virtual ground.

7Measured as voltage settling at midscale transition to

±0.1%; R

L = 50 Ω.

8Measured from 50% point of rising edge of CLOCK signal to 1/2 LSB change in output signal.

9Peak glitch impulse is measured as the largest area under a single positive or negative transient.

10Measured with R

L = 50 Ω and DAC operating in latched mode.

11Data must remain stable for specified time prior to rising edge of CLOCK.

12Data must remain stable for specified time after rising edge of CLOCK.

13SFDR is defined as the difference in signal energy between the full-scale fundamental signal and worst case spurious frequencies in the output spectrum window.

The frequency span is dc-to-Nyquist unless otherwise noted.

14Intermodulation distortion is the measure of the sum and difference products produced when a two-tone input is driven into the DAC. The distortion products

created will manifest themselves at sum and difference frequencies of the two tones.

15Supply voltages should remain stable within

±5% for nominal operation.

Specifications subject to change without notice.

CODE 2

CODE 3

CODE 4

CODE 1

CODE 2

DATA

CODE 1

DATA

CODE 3

DATA

CODE 4

DATA

pwMIN

pwMAX

CLOCK

DATA

ANALOG OUTPUT

CLOCK

ANALOG OUTPUT

tPD

tST

SPECIFIED

ERROR BAND

GLITCH AREA =

1/2 HEIGHT

WIDTH

DETAIL OF SETTLING TIME

Figure 1. Timing Diagrams

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