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AD9483/PCB Folha de dados(PDF) 2 Page - Analog Devices

Nome de Peças AD9483/PCB
Descrição Electrónicos  Triple 8-Bit, 140 MSPS A/D Converter
PDF  26 Pages
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
Logo AD - Analog Devices

AD9483/PCB Folha de dados(HTML) 2 Page - Analog Devices

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–2–
REV. A
AD9483–SPECIFICATIONS
(VCC = +5 V, VDD = +3.3 V, external reference, ENCODE = maximum conversion rate
differential PECL)
Test
AD9483KS-140
AD9483KS-100
Parameter
Temperature
Level
Min
Typ
Max
Min
Typ
Max
Units
RESOLUTION
8
8
Bits
DC ACCURACY
Differential Nonlinearity
+25
°C
I
0.8
1.25/–1.0
0.8
1.25/–1.0
LSB
Full
VI
1.50/–1.0
1.50/–1.0
LSB
Integral Nonlinearity
+25
°C
I
0.9
1.50/–1.50
0.9
1.50/–1.50 LSB
Full
VI
1.75/–1.75
1.75/–1.75 LSB
No Missing Codes
Full
VI
Guaranteed
Guaranteed
Gain Error
1
+25
°CI
±1
±2
±1
±2% FS
Gain Tempco
1
Full
V
160
160
ppm/
°C
ANALOG INPUT
Input Voltage Range
(With Respect to
AIN)
Full
V
±512
±512
mV p–p
Compliance Range AIN or
AIN
Full
V
1.8
3.2
1.8
3.2
V
Input Offset Voltage
+25
°CI
±4
±16
±4
±16
mV
Full
VI
±20
±20
mV
Input Resistance
+25
°C
I
35
83
35
83
k
Ω
Full
VI
25
25
k
Ω
Input Capacitance
+25
°CV
4
4
pF
Input Bias Current
+25
°C
I
17
36
17
36
µA
Full
VI
50
50
µA
Analog Bandwidth, Full Power
+25
°C
V
330
330
MHz
REFERENCE OUTPUT
Output Voltage
Full
VI
+2.4
+2.5
+2.6
+2.4
+2.5
+2.6
V
Temperature Coefficient
Full
V
110
110
ppm/
°C
SWITCHING PERFORMANCE
Maximum Conversion Rate
Full
VI
140
100
MSPS
Minimum Conversion Rate
Full
IV
10
10
MSPS
Encode Pulsewidth High (tEH)
+25
°C
IV
2.8
50
4.0
50
ns
Encode Pulsewidth Low (tEL)
+25
°C
IV
2.8
50
4.0
50
ns
Aperture Delay (tA)
+25
°C
V
1.5
1.5
ns
Aperture Delay Matching
+25
°C
V
100
100
ps
Aperture Uncertainty (Jitter)
+25
°C
V
2.3
2.3
ps rms
Data Sync Setup Time (tSDS)
+25
°CIV
0
0
ns
Data Sync Hold Time (tHDS)
+25
°C
IV
0.5
0.5
ns
Data Sync Pulsewidth (tPWDS)
+25
°C
IV
2.0
2.0
ns
Output Valid Time (tV)
2
Full
VI
4.0
6.3
4.0
6.3
ns
Output Propagation Delay (tPD)
2
Full
VI
8.0
10
8.0
10
ns
Clock Valid Time (tCV)
3
Full
VI
3.8
6.2
3.8
6.2
ns
Clock Propagation Delay (tCPD)
3
Full
VI
8.0
10
8.0
10
ns
Data to Clock Skew (tV–tCV)
Full
VI
–1.0
0
1.0
–1.0
0
1.0
ns
Data to Clock Skew (tPD–tCPD)
Full
VI
–2.0
0
2.0
–2.0
0
2.0
ns
DIGITAL INPUTS
Input Capacitance
+25
°CV
3
3
pF
DIFFERENTIAL INPUTS
Differential Signal Amplitude (VID)
Full
IV
400
400
mV
HIGH Input Voltage (VIHD)
Full
IV
0.4
VCC
0.4
VCC
V
LOW Input Voltage (VILD)
Full
IV
0
0
V
Common-Mode Input (VICM)
Full
IV
1.5
1.5
V
HIGH Level Current (IIH)
Full
VI
1.2
1.2
mA
LOW Level Current (IIL)
Full
VI
1.2
1.2
mA
VREF IN
Input Resistance
+25
°C
V
2.5
2.5
k
Ω



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