AD9225ARS datasheet(21/24 Pages) AD

21 / 24 page

AD9225

–21–

REV. A

The digital activity on the AD9225 chip falls into two general

categories: correction logic, and output drivers. The internal

correction logic draws relatively small surges of current, mainly

during the clock transitions. The output drivers draw large

current impulses while the output bits are changing. The size

and duration of these currents are a function of the load on the

output bits: large capacitive loads are to be avoided. Note, the

internal correction logic of the AD9225 is referenced to AVDD

while the output drivers are referenced to DRVDD.

The decoupling shown in Figure 43, 0.1

µF ceramic chip capaci-

tors and a 10

µF tantalum are appropriate for a reasonable

capacitive load on the digital outputs (typically 20 pF on each

pin). Applications involving greater digital loads should consider

increasing the digital decoupling proportionally, and/or using

external buffers/latches.

0.1 F

DRVDD

DRVSS

AD9225

10 F

Figure 43. Digital Supply Decoupling

A complete decoupling scheme will also include large tantalum

or electrolytic capacitors on the PCB to reduce low frequency

ripple to negligible levels. Refer to the AD9225/AD9225EB

schematic and layouts in Figures 44–50 for more information

regarding the placement of decoupling capacitors.

AD9225ARS Folha de dados(PDF) 21 Page - Analog Devices