AD8061ART datasheet(13/16 Pages) AD

13 / 16 page

AD8061/AD8062/AD8063

–13–

REV. C

For signals approaching the minus supply and inverting gain

and high positive gain conﬁgurations, the headroom limit will be

the output stage. The AD806x ampliﬁers use a common emitter

style output stage. This output stage maximizes the available

output range, limited by the saturation voltage of the output

transistors. The saturation voltage increases with the drive

current the output transistor is required to supply, due to the

output transistors’ collector resistance. The saturation voltage

can be estimated using the equation VSAT = 25 mV + IO

× 8 Ω,

where IO is the output current, and 8

Ω is a typical value for the

output transistors’ collector resistance.

TIME – ns

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

2V TO 3V STEP

2.1V TO 3.1V STEP

2.2V TO 3.2V STEP

2.3V TO 3.3V STEP

2.4V TO 3.4V STEP

Figure 5. Output Rising Edge for 1 V Step at Input Head-

room Limits, G = 1, VS = 5 V, 0 V

As the saturation point of the output stage is approached, the

output signal will show increasing amounts of compression and

clipping. As in the input headroom case, the higher frequency

signals require a bit more headroom than the lower frequency

signals. TPCs 11, 12, and 13 illustrate the point, plotting typical

distortion versus output amplitude and bias for gains of 2 and 5.

Overload Behavior and Recovery

Input

The speciﬁed input common-mode voltage of the AD806x is

–200 mV below the negative supply to within 1.8 V of the posi-

tive supply. Exceeding the top limit results in lower bandwidth

and increased settling time as seen in Figures 4 and 5. Push-

ing the input voltage of a unity gain follower beyond 1.6 V within

the positive supply leads to the behavior shown in Figure 6—an

increasing amount of output error as well as much increased

settling time. Recovery time from input voltages 1.6 V or closer

to the positive supply is about 35 ns, which is limited by the

settling artifacts caused by transistors in the input stage com-

ing out of saturation.

The AD806x family does not exhibit phase reversal, even for input

voltages beyond the voltage supply rails. Going more than 0.6 V

beyond the power supplies will turn on protection diodes at the

input stage, which will greatly increase the device’s current draw.

TIME – ns

2.1

2.3

100

VOLTAGE STEP

FROM 2.4V TO 3.4V

2.5

2.7

2.9

3.1

3.3

3.5

3.7

VOLTAGE STEP

FROM 2.4V TO 3.6V

VOLTAGE STEP

FROM 2.4V TO 3.8V,

4V AND 5V

200

300

400

500

600

Figure 6. Pulse Response for G = 1 Follower, Input Step

Overloading the Input Stage

Output

Output overload recovery is typically within 40 ns after the

ampliﬁer’s input is brought to a nonoverloading value. Figure

7 shows output recovery transients for the ampliﬁer recovering

from a saturated output from the top and bottom supplies to a

point at midsupply.

TIME – ns

–0.20

OUTPUT VOLTAGE

5V TO 2.5V

0.20

0.60

1.0

1.4

1.8

2.2

2.6

3.0

3.4

3.8

4.2

4.6

5.0

3040506070

OUTPUT VOLTAGE

0V TO 2.5V

INPUT VOLTAGE

EDGES

2.5V

VIN

Figure 7. Overload Recovery, G = –1, VS = 5 V

CAPACITIVE LOAD DRIVE

The AD806x family is optimized for bandwidth and speed, not

for driving capacitive loads. Output capacitance will create a

pole in the ampliﬁer’s feedback path, leading to excessive

peaking and potential oscillation. If dealing with load capaci-

tance is a requirement of the application, the two strategies to

consider are (1) using a small resistor in series with the

ampliﬁer’s output and the load capacitance and (2) reducing

the bandwidth of the ampliﬁer’s feedback loop by increasing the

overall noise gain.

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