ACE5372

Low Power Real-Time Clock (RTC)

VER 1.3

12



Level mode

7. Control Register 2 ( at internal address FH )

D7

D6

D5

D4

D3

D2

D1

D0

Operation

-

-

12_/24

ADJ

CLEN_

CTFG

AAFG

BAFG

Write

0

0

12_/24

XSTP

CLEN_

CTFG

AAFG

BAFG

Read

0

0

Undefined

1

0

0

0

0

Default

*The default means read value when XSTP bit is set to “1” by starting up from 0V, or supply voltage drop, etc.

12/24

12/24-hour Time Display System Selection bit

12/24

Description

0

12-hour time display system

1

24-hour time display system

Being set this bit at “0” indicates 12-hour display system while “1” indicates 24-hour system.

Time Display Digit Table

24-hour time display

system

12-hour time display

system

24-hour time display

system

12-hour time display

system

00

12(AM12)

12

32(PM12)

01

01(AM1)

13

21(PM1)

02

02(AM2)

14

22(PM2)

03

03(AM3)

15

23(PM3)

04

04(AM4)

16

24(PM4)

05

05(AM5)

17

25(PM5)

06

06(AM6)

18

26(PM6)

07

07(AM7)

19

27(PM7)

08

08(AM8)

20

28(PM8)

09

09(AM9)

21

29(PM9)

10

10(AM10)

22

30(PM10)

11

11(AM11)

23

31(PM11)