CY8C58LP datasheet(7/122 Pages) CYPRESS

7 / 122 page

PRELIMINARY

PSoC® 5LP: CY8C58LP Family

Datasheet

Document Number: 001-84932 Rev. **

Page 7 of 122

Figure 2-4. 100-pin TQFP Part Pinout

Figure 2-5 on page 8 and Figure 2-6 on page 9 show an example schematic and an example PCB layout, for the 100-pin TQFP part,

for optimal analog performance on a two-layer board.

■ The two pins labeled VDDD must be connected together.

■ The two pins labeled VCCD must be connected together, with capacitance added, as shown in Figure 2-5 and “Power System”

section on page 24. The trace between the two VCCD pins should be as short as possible.

■ The two pins labeled VSSD must be connected together.

For information on circuit board layout issues for mixed signals, refer to the application note, AN57821 - Mixed Signal Circuit Board

Layout Considerations for PSoC® 3 and PSoC 5.

TQFP

(TRACEDATA[1], GPIO) P2[5]

(TRACEDATA[2], GPIO) P2[6]

(TRACEDATA[3], GPIO) P2[7]

(I2C0: SCL, SIO) P12[4]

(I2C0: SDA, SIO) P12[5]

(GPIO) P6[4]

(GPIO) P6[5]

(GPIO) P6[6]

(GPIO) P6[7]

VSSB

IND

VBOOST

VBAT

VSSD

XRES

(GPIO) P5[0]

(GPIO) P5[1]

(GPIO) P5[2]

(GPIO) P5[3]

(TMS, SWDIO, GPIO) P1[0]

(TCK, SWDCK, GPIO) P1[1]

(Configurable XRES, GPIO) P1[2]

(TDO, SWV, GPIO) P1[3]

(TDI, GPIO) P1[4]

(NTRST, GPIO) P1[5]

VDDIO0

P0[3] (GPIO, OPAMP0-, EXTREF0)

P0[2] (GPIO, OPAMP0+, SAR1 EXTREF)

P0[1] (GPIO, OPAMP0OUT)

P0[0] (GPIO, OPAMP2OUT)

P4[1] (GPIO)

P4[0] (GPIO)

P12[3] (SIO)

P12[2] (SIO)

VSSD

VDDA

VSSA

VCCA

P15[3] (GPIO, KHZ XTAL: XI)

P15[2] (GPIO, KHZ XTAL: XO)

P12[1] (SIO, I2C1: SDA)

P12[0] (SIO, I2C1: SCL)

P3[7] (GPIO, OPAMP3OUT)

P3[6] (GPIO, OPAMP1OUT)

Lines show VDDIO

to I/O supply

association

Notes

6. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.

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