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RT8859M Folha de dados(PDF) 21 Page - Richtek Technology Corporation |
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RT8859M Folha de dados(HTML) 21 Page - Richtek Technology Corporation |
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21 / 51 page ![]() RT8859M 21 DS8859M-05 July 2012 www.richtek.com © Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Parameter Symbol Test Conditions Min Typ Max Unit Thermal Throttling VRHOT Output Voltage VVRHOT IVRHOT = 10mA -- -- 0.13 V Current Monitor Current Monitor Maximum Output Voltage in Operating Range VIMON VDAC = 1V, VFB − VCC_SENSE = 100mV, RIMONFB = 10kΩ, RIMON = 330kΩ 3.2 3.3 3.4 V High Impedance Output PWMx, ALERT, VRx_RDY, VRHOT ILEAK_OUT −1 -- 1 μA PWM Driving Capability PWM Source Resistor RPWM_SOURCE -- 30 -- Ω PWM Sink Resistor RPWM_SINK -- 15 -- Ω DVID, DVIDA, ICCMAX, ICCMAXA, and TMPMAX Pin Current Current Sourcing Out from DVIDx Pin to GND IDVIDx During dynamic VID fast event 6 8 10 μA Current Sinking In from 5V to ICCMAX Pin IICCMAX After VR_RDY -- 16 -- μA Current Sourcing Out from ICCMAXA Pin to GND IICCMAXA After VRA_RDY -- 128 -- μA Current Sinking In from 5V to TMPMAX Pin ITMPMAX After VR_RDY -- 16 -- μA DVID and DVIDA Maximum Voltage Maximum Allowable Voltage at DVIDx Pin VDVIDx_MAX During Dynamic VID Event -- -- 2 V SVID SVID Frequency fSVID 5 25 26.25 MHz SVID Clock to Data Delay tCO 4 -- 8.3 ns Setup Time of VDIO tSU 7 -- -- ns Hold Time of VDIO tHLD 14 -- -- ns VINITIAL Setting VSETINI0 For VINITIAL = 0V 0 -- 8 VSETINI0_9 For VINITIAL = 0.9V 17 -- 20 VSETINI1_0 For VINITIAL = 1V 32.5 -- 42.5 VSETINI1_1 For VINITIAL = 1.1V 57.5 -- 67.5 SETINIx Threshold Voltage VSETINI1_5 For VINITIAL = 1.5V 82.5 -- 100 %VCC ADD Threshold Logic-Low VIL Set SVID address 0000 0001 -- -- 0.35 Logic-Medium VIM Set SVID address 0010 0011 0.7 -- 3 ADD Input Threshold Voltage Logic-High VIH Set SVID address 0100 0101 VCC − 0.2 -- -- V |
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