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WM8253SCDS/V Folha de dados(PDF) 8 Page - Wolfson Microelectronics plc |
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WM8253SCDS/V Folha de dados(HTML) 8 Page - Wolfson Microelectronics plc |
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8 / 27 page ![]() WM8253 Production Data w PD, Rev 4.1, August 2011 8 INPUT VIDEO SAMPLING Figure 1 Input Video Timing Note: 1. See Page 15 (Programmable VSMP Detect Circuit) for video sampling description. Test Conditions AVDD = DVDD1 = DVDD2 = 3.3V, AGND = DGND = 0V, TA = 25C, MCLK = 36MHz unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS MCLK period tPER 27.7 ns MCLK high period tMCLKH 13.85 ns MCLK low period tMCLKL 13.85 ns VSMP period tVPER 300 1000 ns VSMP set-up time tVSMPSU 6 ns VSMP hold time tVSMPH 3 ns Video level set-up time tVSU 10 ns Video level hold time tVH 3 ns Reset level set-up time tRSU 10 ns Reset level hold time tRH 3 ns Notes: 1. tVSU and tRSU denote the set-up time required after the input video signal has settled. 2. Parameters are measured at 50% of the rising/falling edge. OUTPUT DATA TIMING MCLK OP[3:0] t PD t PD Figure 2 Output Data Timing MCLK VSMP INPUT VIDEO t PER t VSMPSU t VSMPH t VSU t VH t RSU t RH t MCLKL t MCLKH t VPER t RSU |
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