WM8761

Production Data

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PD, Rev 4.6, October 2011

9

POWER ON RESET (POR)

The WM8761 has an internal power-on-reset (POR) circuit which is used to reset the digital logic

into a default state after power up. A block diagram of the reset circuit is shown in Figure 3

Figure 3 Block Diagram of Power-On-Reset

The active low reset signal NPOR will be asserted low until VDD=2.4V, which means VMID rises

to 1.2V. When this threshold has been reached, then the NPOR is released and the digital

interface has been reset. This is illustrated in the diagram shown in Figure 4.

Figure 4 Generation of Internal NPOR at Power-On-Reset

Figure 5 illustrates the NPOR generation when the power is removed.