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CLVC16373AMDLREP Folha de dados(PDF) 2 Page - Texas Instruments |
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CLVC16373AMDLREP Folha de dados(HTML) 2 Page - Texas Instruments |
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2 / 10 page ![]() www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) 1OE 1LE 1D1 To Seven Other Channels 1Q1 C1 1D 1 48 47 2 2OE 2LE 2D1 To Seven Other Channels 2Q1 C1 1D 24 25 36 13 SN74LVC16373A-EP 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS SCAS825 – JUNE 2006 OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. FUNCTION TABLE INPUTS OUTPUT Q OE LE D L H H H L H L L L L X Q0 H X X Z LOGIC DIAGRAM (POSITIVE LOGIC) 2 Submit Documentation Feedback |
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