TNETX3270 datasheet(55/66 Pages) TI1

Nome de Peças	TNETX3270

Descrição Electrónicos	ThunderSWITCHE 24/3 ETHERNETE SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

PDF	66 Pages

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Fabricante Electrônico	TI1 [Texas Instruments]

Página de início	http://www.ti.com

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55 / 66 page

TNETX3270

ThunderSWITCH

™ 24/3 ETHERNET™ SWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

10-/100-Mbit/s transmit ports (24, 25, and 26)

timing requirements (see Figure 15)

NO.

MIN

MAX

UNIT

tc(MxxTCLK)

Cycle time, MxxTCLK

tw(MxxTCLKL)

Pulse duration, MxxTCLK low

tw(MxxTCLKH)

Pulse duration, MxxTCLK high

operating characteristics over recommended operating conditions (see Note 8 and Figure 15)

NO.

PARAMETER

MIN

MAX

UNIT

4†

td(MxxTXD)

Delay time, from MxxTCLK

↑ to MxxTXD3–MxxTXD0 valid

4†

td(MxxTXEN)

Delay time, from MxxTCLK

↑ to MxxTXEN valid

4†

td(MxxTXER)

Delay time, from MxxTCLK

↑ to MxxTXER valid

† xx = ports 24, 25, and 26

NOTE 8: Both MxxCRS and MxxCOL are driven asynchronously by the PHY. MxxTXD3–MxxTXD0 is driven by the reconciliation sublayer

synchronous to the MxxTCLK. MxxTXEN is asserted and deasserted by the reconciliation sublayer synchronous to the MxxTCLK rising

edge. MxxTXER is driven synchronous to the rising edge of MxxTCLK.

MxxTXD3–MxxTXD0

MxxTXEN

MxxTXER

(outputs)

MxxTCLK

(input)

Figure 15. 10-/100-Mbit/s Transmit Ports

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