DAC1403D160 3

© IDT 2012. All rights reserved.

Product data sheet

Rev. 03 — 2 July 2012

6 of 18

Integrated Device Technology

DAC1403D160

Dual 14 bits DAC, up to 160 MHz, 2 x interpolating

7. Functional description

The Digital-to-Analog Converter (DAC) is a segmented architecture composed of a 7-bit

thermometer sub-DAC and the remaining 7-bit in a binary weighted sub-DAC.

The device produces two complementary current outputs on both channels, respectively

pins IOUT/IOUTN and QOUT/QOUTN which need to be connected via a load resistor to

the ground.

Figure 3 shows the equivalent analog output circuit of one DAC, which consists of a

parallel combination of PMOS current sources and associated switches for each segment.

The cascade source configuration enables the increasing of the output impedance of the

source and set to improve the dynamic performance of the DAC by introducing less

distortion.

Figure 4 shows the internal reference configuration. In this case the bias current is given

by the output of the internal regulator connected to the inverting input of the internal

pins IVIRES and QVIRES. Thus the output current of the two DACs is typically fixed to

20 mA with an appropriate choice of these resistors. This configuration is optimal for

temperature drift compensation because the band gap can be matched with the voltage

on the feedback resistors.







-----------------------------------------

=

The output current can also be adjusted by imposing an external reference voltage to the

inverting input pin GAPOUT and disabling the internal band gap with pin GAPD set to

HIGH. At a voltage lower than 1.2 V the current can be set at values lower than 20 mA.

The input references at pins IVIRES and QVIRES may also be driven by separate

reference voltages to adjust independently the two DAC currents.

014aaa514

AGND

AGND

IOUT/QOUT

IOUTN/QOUTN

DAC1403D160

014aaa515

QVIRES

IVIRES

GAPOUT

AGND

GAPD

INTERNAL

BAND GAP

I DAC current

sources array

DAC1403D160

Q DAC current

sources array

Fig 3. Equivalent analog output circuit

Fig 4. Internal reference configuration