L6472PD datasheet(15/69 Pages) STMICROELECTRONICS

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L6472

Electrical characteristics

Doc ID 022729 Rev 1

15/69

tcpwu

Charge pump power-on and

wake-up time

Power bridges disabled, Cp =

10nF, Cboot = 220nF

650

µs

Internal voltage regulator

VREG

Voltage regulator output

voltage

2.9

3.2

IREG

Voltage regulator output

current

VREG, drop

Voltage regulator output

voltage drop

IREG = 40mA

IREG,STBY

Voltage regulator standby

output current

Integrated analog-to-digital converter

NADC

Analog-to-digital converter

resolution

bit

VADC,ref

Analog-to-digital converter

reference voltage

VREG

Analog-to-digital converter

sampling frequency

fOSC/

512

kHz

Accuracy depends on oscillator frequency accuracy.

Tested at 25 °C in a restricted range and guaranteed by characterization.

Rise and fall time depends on motor supply voltage value. Refer to SRout values in order to evaluate the

actual rise and fall time.

Not valid for the STBY/RST pin which has an internal pull-down resistor.

Not valid for the SW and CS pins which have an internal pull-up resistor.

FLAG, BUSY and SYNC open drain outputs included.

See Figure 20 – SPI timings diagram for details.

Table 5.

Electrical characteristics (continued)

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

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