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AD7457BRT-R2 Folha de dados(PDF) 15 Page - Analog Devices |
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AD7457BRT-R2 Folha de dados(HTML) 15 Page - Analog Devices |
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15 / 20 page ![]() AD7457 Rev. A | Page 15 of 20 Table 5. SPORT0 Configuration Bit Setting Comment/Description ISCLK 1 Serial clock is generated internally SLEN 1111 16 bits of conversion data RFSR 0 Receive frame sync required every word TFSR Don’t care Not used IRFS 0 RFS is set to be an input and is generated externally. ITFS Don’t care Not used RFSW 1 Alternate receive framing TFSW Don’t care Not used INVRFS 0 RFS is active high INVTFS Don’t care Not used SPORT0 is configured by setting the bits in its control register, as listed in Table 5. The flag to generate the CS signal is generated by SPORT1. It is connected to both the ADC and the RFS input of SPORT0 to provide the frame sync signal for the DSP. |
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