SP8121JS datasheet(4/13 Pages) SIPEX

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SP8121DS/02

SP8121 Monolithic, 12-Bit Data Acquisition System

SP8121 PINOUT

116

234567

9 10 11 12 13 14 15

23 22 21 20 19 18

30 29 28 27 26 25

32 31

CONTROL

LOGIC

12-BIT ADC

8-CHANNEL

MULTIPLEXER

DECODE

REF

SP8121 CONTROL TRUTH TABLE

R/C

OPERATION

L->H

Start Conversion

H ->L

Start Conversion

Enable 12-bit Output

(when STATUS=0)

SP8121 MULTIPLEXER TRUTH TABLE

LATCH MA

OPERATION

H -> L

O Selected

H -> L

1 Selected

H -> L

2 Selected

H -> L

3 Selected

H -> L

4 Selected

H -> L

5 Selected

H -> L

6 Selected

H -> L

7 Selected

Prev. CH “n” Held

SP8121 PINOUT

STATUS — Identifies valid data output; goes to

logic high during conversion; goes to logic low

when conversion is completed and data is valid

R/C — Read/Convert — Initiates conversion on

the high-to-low transition; logic low discon-

nects data bus; logic high initiates read

CE — Chip Enable — Logic low disables read

or convert; logic high enables read or convert

LATCH — MUX Address Latch — Logic high

to low transition captures MUX address on

MUX address lines

0, MA1, MA2 — MUX Address 0, 1 & 2 —

Selects analog input channels CH

0 through CH7

0 through DB11 — Data Outputs — Logic

high is binary true; logic low binary false

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