UCD3138RHAR datasheet(26/68 Pages) TI1

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Error ADC

(Front End)

Filter

Digital

PWM

EAP

EAN

DPWMA

DPWMB

UCD3138

SLUSAP2 A – MARCH 2012 – REVISED MARCH 2012

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Table 4-1. Interrupt Priority Table (continued)

MODULE COMPONENT OR

NAME

DESCRIPTION

PRIORITY

DPWM3

Same as DPWM1

DPWM2

Same as DPWM1

1) Every (1-256) switching cycles

DPWM1

2) Fault Detection

3) Mode switching

DPWM0

Same as DPWM1

EXT_FAULT_INT

External Faults

Fault pin interrupt

SYS_SSI_INT

System Software

System software interrupt

31 (highest)

4.4

Peripherals

4.4.1

Fusion Digital Power Peripherals

At the core of the UCD31XX controller are 3 Fusion Digital Power Peripherals (FDPP). Each FDPP can be

configured to drive from one to eight DPWM outputs. Each FDPP consists of:

•

Differential input error ADC (EADC) with sophisticated controls

•

Hardware accelerated digital 2-pole/2-zero PID based compensator

•

Digital PWM module with support for a variety of topologies

These can be connected in many different combinations, with multiple filters and DPWMs. They are

capable of supporting functions like input voltage feed forward, current mode control, and constant

current/constant power, etc.. The simplest configuration is shown in the following figure:

4.4.1.1

Front End

The EADC module can be programmed to produce an inverting or non-inverting error relative to the

voltage set by the EADC DAC. It also has a successive approximation mode, which can be used to

measure absolute voltage. In this case, the SAR module controls the EADC and EADC-DAC to determine

the absolute voltage.

The EADC module is shown in Figure 4-1. It contains a differential switch capacitor amplifier. This enables

remote sense voltage measurements, using the external EAP and EAN pins. The output of this stage is

fed into a second differential amplifier with a reference driven by an internal 10-bit DAC. The gain of this

stage is controlled by the AFE register. AFE can have values of 0, 1, 2 or 3 which correspond to an

analog gain of 1, 2, 4 or 8 respectively. The EADC has a maximum sense voltage value of 248 mV and a

minimum sense value of -256 mV with 8 mV resolution. The analog AFE gain stage effectively makes this

resolution programmable to be 8mV, 4 mV, 2 mV or 1 mV. Finally, the EADC output is shifted by 0. 1. 2 or

3 times; this is done to attenuate the digital signal by 1, 2, 4 or 8 times. Both the analog gain value and

the digital gain values are determined from the AFE gain setting. Therefore, the total gain of this stage

always remains the same and the resolution is always 1 mv/bit.

In addition, the user has the option of enabling an automatic resolution selection algorithm ("gear shifter").

This algorithm will automatically select the finest EADC resolution that can measure the voltage across

EAP0 and EAN0. This feature is only available on Front End 0.

Functional Overview

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