UCD3138RHAT datasheet(27/68 Pages) TI1

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EAP0

EAN0

DAC0

EADC

4 bit dithering gives 14 bits of effective resolution

97.65625 µV/LSB effective resolution

6 bit ADC

8 mV/LSB

Signed 9 bit result

(error) 1 mV /LSB

AFE_GAIN

10 bit DAC

1.5625 mV/LSB

Value

Dither

CPCC

Filter x

Ramp

SAR/Prebias

Absolute Value

Calculation

Averaging

10 bit result

1.5625 mV/LSB

3-AFE_GAIN

Peak Current Mode

Comparator

Peak Current

Detected

AFE_GAIN

UCD3138

www.ti.com

SLUSAP2 A – MARCH 2012 – REVISED MARCH 2012

Figure 4-1. EADC Module

The EADC control logic receives the sample request from the DPWM module for initiating an EADC

conversion. EADC control circuitry captures the EADC-9-bit-code and strobes the digital compensator for

processing of the representative error.

4.4.1.2

DPWM Module

The DPWM module represents one complete PWM channel with 2 independent outputs, A and B. Multiple

DPWM modules within the UCD3138 system can be configured to support all key power topologies.

DPWM modules can be used as independent PWM outputs, each controlling one power supply output

voltage rail. It can also be used as a synchronized PWM—with user selectable phase shift between the

PWM channels to control power supply outputs with multiphase or interleaved PWM configurations.

The output of the compensator feeds the high resolution DPWM module. The DPWM module produces

the pulse width modulated outputs for the power stage switches. The compensator calculates the

necessary duty ratio as a 24-bit number in Q23 fixed point format (23 bit integer with 1 sign bit). This

represents a value within the range 0.0 to 1.0. This duty ratio value is multiplied by the period of the PWM

output to generate the on time of the corresponding PWM output. The resolution of the PWM ON time is

250 psec.

Each DPWM module can be synchronized to another module or to an external sync signal. An input

SYNC signal causes a PWM ramp timer to reset. The SYNC signal outputs—from each of the four DPWM

modules—occur when the ramp timer crosses a programmed threshold. In this way the phase of the PWM

outputs for multiple power stages can be tightly controlled.

The DPWM logic is probably the most complex of the Digital Fusion Peripherals. It takes the output of the

compensator and converts it into the correct PWM output for several power supply topologies. It provides

for programmable dead times and cycle adjustments for current balancing between phases. It controls the

triggering of the EADC. It can synchronize to other DPWMs or to external sources. It can provide

synchronization information to other DPWMs or to external recipients. In addition, it interfaces to several

fault handling circuits. Some of the control for these fault handling circuits is in the DPWM registers. Fault

handling is covered in the Fault Mux section.

Each DPWM module supports the following features:

•

Dedicated 14 bit time-base with period and frequency control

Functional Overview

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