UCD3138RGCT datasheet(22/68 Pages) TI1

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UCD3138

SLUSAP2 A – MARCH 2012 – REVISED MARCH 2012

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Functional Overview

4.1

ARM Processor

The ARM7TDMI-S processor is a synthesizable member of the ARM family of general purpose 32-bit

microprocessors. The ARM architecture is based on RISC (Reduced Instruction Set Computer) principles

where two instruction sets are available. The 32-bit ARM instruction set and the 16-bit Thumb instruction

set. The Thumb instruction allows for higher code density equivalent to a 16-bit microprocessor, with the

performance of the 32-bit microprocessor.

The three-staged pipelined ARM processor has fetch, decode and execute stage architecture. Major

blocks in the ARM processor include a 32-bit ALU, 32 x 8 multiplier, and a barrel shifter. A JTAG port is

also available for firmware debugging.

4.2

Memory

The UCD31xx (ARM7TDMI-S) is a Von-Neumann architecture, where a single bus provides access to all

of the memory modules. All of the memory module addresses are sequentially aligned along the same

address range. This is applies to program flash, data flash, ROM and all other peripherals.

Within the UCD31xx architecture, there is a 1024x32-bit Boot ROM that contains the initial firmware

startup routines for PMBUS communication and non-volatile (FLASH) memory download. This boot ROM

is executed after power-up-reset checks if there is a valid FLASH program written. If a valid program is

present, the ROM code branches to the main FLASH-program execution.

UCD31xx also supports customization of the boot program by allowing an alternative booting routine to be

executed from program FLASH. This feature enables assignment of a unique address to each device;

therefore, enabling firmware reprogramming even when several devices are connected on the same

communication bus.

Two separate FLASH memory areas are present inside the device. The 32 kB Program FLASH is

organized as an 8 k x 32 bit memory block and is intended to be for the firmware program. The block is

configured with page erase capability for erasing blocks as small as 1kB per page, or with a mass erase

for erasing the entire program FLASH array. The FLASH endurance is specified at 1000 erase/write

cycles and the data retention is good for 100 years. The 2 kB data FLASH array is organized as a 512 x

32 bit memory (32 byte page size). The Data FLASH is intended for firmware data value storage and data

logging. Thus, the Data FLASH is specified as a high endurance memory of 20 k cycles with embedded

error correction code (ECC).

For run time data storage and scratchpad memory, a 4 kB RAM is available. The RAM is organized as a 1

k x 32 bit array.

4.2.1

CPU Memory Map and Interrupts

When the device comes out of power-on-reset, the data memories are mapped to the processor as

follows:

4.2.1.1

Memory Map (After Reset Operation)

Address

Size

Module

0x0000_0000 – 0x0000_FFFF

16 X 4K

Boot ROM

In 16 repeated blocks of 4K each

0x0001_0000 – 0x0001_7FFF

32K

Program Flash

0x0001_8800 – 0x0001_8FFF

Data Flash

0x0001_9000 – 0x0001_9FFF

Data RAM

Functional Overview

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