ADP1047ARQZ-R7 datasheet(63/84 Pages) AD

63 / 84 page

Data Sheet

ADP1047/ADP1048

Rev. 0 | Page 63 of 84

Table 81. Register 0xFE13—PWM2 Falling Edge Setting (PWM2 Pin)

Bits

Bit Name

R/W

Description

[7:4]

RSVD

Reserved.

[3:2]

R/W

These bits contain the two LSBs of the 10-bit t2 time. This value is always used with the eight

bits of Register 0xFE12, which contains the eight MSBs of the t2 time.

Modulate enable

R/W

1 = PWM modulation acts on the t2 edge.

0 = no PWM modulation of the t2 edge.

t2 sign

R/W

1 = positive sign. Increase of PWM modulation moves t2 right.

0 = negative sign. Increase of PWM modulation moves t2 left.

PWM_SET REGISTER

Table 82. Register 0xFE14—PWM_SET

Bits

Bit Name

R/W

Description

[7:5]

RSVD

Reserved.

ADP1048 operation

R/W

Reserved for the ADP1048 only.

1 = bridgeless PFC operation.

0 = interleaved PFC operation.

PWM resolution

R/W

1 = 5 ns.

0 = 40 ns.

PWM enable

R/W

1 = disable the PWM output.

0 = enable the PWM output.

PWM2 enable

R/W

1 = disable the PWM2 output.

0 = enable the PWM2 output.

Go button

R/W

The PWM settings are updated during the transition of this bit from low to high.

PWM_LIMIT REGISTER

Table 83. Register 0xFE15—PWM_LIMIT

Bits

Bit Name

R/W

Description

[7:4]

Limit minimum

on time

R/W

These bits set the minimum on time for the PWM outputs in steps of 80 ns: 0000 = 0 ns and

1111 = 1200 ns.

[3:0]

Limit minimum

off time

R/W

These bits set the minimum off time for the PWM outputs: 0000 = 40 ns, 0001 = 80 ns, 1111 =

1200 ns.

RTD ADC OFFSET TRIM SETTING (MSB) REGISTER

This register must be unlocked for write access; see Table 61.

Table 84. Register 0xFE16—RTD ADC Offset Trim Setting (MSB)

Bits

Bit Name

R/W

Description

[7:2]

RSVD

R/W

Reserved.

Trim polarity

R/W

1 = negative offset trim is introduced.

0 = positive offset trim is introduced.

RTD ADC offset trim

R/W

This bit is the MSB of the 9-bit value that sets the amount of offset trim applied to the RTD ADC

reading. The LSBs are specified in Register 0xFE17.

RTD ADC OFFSET TRIM SETTING (LSB) REGISTER

This register must be unlocked for write access; see Table 61.

Table 85. Register 0xFE17—RTD ADC Offset Trim Setting (LSB)

Bits

Bit Name

R/W

Description

[7:0]

RTD ADC offset trim

R/W

These eight bits are the LSBs of the 9-bit value that sets the amount of offset trim applied to

the RTD ADC reading. The MSB is specified in Register 0xFE16, Bit 0.

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