ADP1046ACPZ-R7 datasheet(57/96 Pages) AD

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Data Sheet

ADP1046

Rev. 0 | Page 57 of 96

Bits

Bit Name

R/W

Description

Volt-second balance

modulation

R/W

This bit specifies the maximum amount of modulation from volt-second balance.

0 = ±80 ns maximum.

1 = ±160 ns maximum.

[1:0]

Volt-second balance

gain setting

R/W

These bits set the gain of the volt-second balance circuit. The gain can be changed by a factor of

64. When these bits are set to 00, it takes approximately 700 ms to achieve volt-second balance.

When these bits are set to 11, it takes approximately 10 ms to achieve volt-second balance.

Bit 1

Bit 0

Volt-Second Balance Gain

Table 41. Register 0x29—Share Bus Bandwidth

Bits

Bit Name

R/W

Description

[7:5]

Reserved

R/W

Reserved.

Bit stream

R/W

1 = the current sense ADC reading is output on the SHAREo pin. This bit stream can be used for

analog current sharing.

0 = the digital share bus signal is output on the SHAREo pin. This signal can be used for digital

current sharing.

Current share select

R/W

1 = CS1 reading used for current share.

0 = CS2 reading used for current share.

[2:0]

Share bus bandwidth

R/W

These bits determine the amount of bandwidth dedicated to the share bus. The value 000 is

the lowest possible bandwidth, and the value 111 is the highest possible bandwidth.

Table 42. Register 0x2A—Share Bus Setting

Bits

Bit Name

R/W

Description

[7:4]

Number of bits

dropped by master

R/W

These bits determine how much a master device reduces its output voltage to maintain

current sharing.

[3:0]

Bit difference between

master and slave

R/W

These bits determine how closely a slave tries to match the current of the master device. The

higher the setting, the larger the voltage difference that satisfies the current sharing criteria.

Table 43. Register 0x2B—Temperature Gain Trim

Bits

Bit Name

R/W

Description

Gain polarity

R/W

1 = negative gain is introduced.

0 = positive gain is introduced.

[6:0]

Gain trim

R/W

This register calibrates the RTD ADC gain. It calibrates for errors in the ADC.

Table 44. Register 0x2C—PSON/Soft Start

Bits

Bit Name

R/W

Description

[7:6]

PS_ON setting

R/W

These bits determine which signal is used by the ADP1046 as the PS_ON control.

Bit 7

Bit 6

PS_ON Setting

The ADP1046 is always on.

Hardware PSON pin is used to enable or disable the power supply.

Software PS_ON bit (Bit 5) is used to enable or disable the power supply.

Both the software PS_ON bit and the hardware PSON pin must be enabled

before the ADP1046 is enabled.

PS_ON

R/W

Software PS_ON bit.

0 = power supply off.

1 = power supply on.

[4:3]

PS_ON delay

R/W

These bits set the time from when the PS_ON control signal is set to when the soft start begins.

Bit 4

Bit 3

Typical Delay (sec)

0.5

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