ADL5324ARKZ-R7 datasheet(13/20 Pages) AD

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Data Sheet

ADL5324

Rev. 0 | Page 13 of 20

APPLICATIONS INFORMATION

BASIC LAYOUT CONNECTIONS

The basic connections for operating the ADL5324 are shown

in Figure 34. Table 6 lists the required matching components.

Capacitors C1, C2, and C3 are Murata GRM615 series (0402

size) High Q capacitors and C7 is a Murata GRM155 series

(0402 size). Inductor L1 is a Coilcraft 0603CS series (0603

size). For all frequency bands, the placement of C1 and C2 are

critical. The placement of C3 becomes critical for the following

bands: 1880 MHz to 1990 MHz, 2110 MHz to 2170 MHz,

2300 MHz to 2400 MHz, 2570 MHz to 2690 MHz. and 3500 MHz

to 3600 MHz. For operation from 420 MHz to 494 MHz, 728 MHz

to 768 MHz, and 869 MHz to 960 MHz, R2 is replaced with a

Coilcraft (0402 size) High Q inductor. Table 7 lists the recom-

mended component placement for various frequencies.

A 5 V dc bias is supplied through L1, which is connected to

RFOUT (Pin 3). In addition to C4, 10 nF and 10 μF power

supply decoupling capacitors are also required. The typical

current consumption for the ADL5324 is 140 mA.

(2)

ADL5324

C6 10µF

C5 10nF

C4 100pF

15nH

VSUP

GND

RFIN

20pF

C23

2.2pF

RFOUT

C13

2pF

C33

2.4pF

λ12

λ22

1SEE THE RECOMMENDED COMPONENTS FOR BASIC CONNECTIONS TABLE

FOR FREQUENCY-SPECIFIC COMPONENTS.

2SEE TABLE 6 FOR RECOMMENDED COMPONENT SPACING.

3C1, C2, AND C3 ARE MURATA HIGH Q CAPACITORS GRM615 SERIES.

0Ω

Figure 34. Basic Connections

SOLDERING INFORMATION AND RECOMMENDED

PCB LAND PATTERN

Figure 35 shows the recommended land pattern for the ADL5324.

To minimize thermal impedance, the exposed paddle on the

SOT-89 package underside is soldered to a ground plane along

with Pin 2. If multiple ground layers exist, they should be

stitched together using vias. For more information on land

pattern design and layout, refer to the Application Note AN-772,

A Design and Manufacturing Guide for the Lead Frame Chip

Scale Package (LFCSP).

This land pattern, on the ADL5324 evaluation board, provides

a measured thermal resistance (θJA) of 37°C/W. To measure θJA,

the temperature at the top of the SOT-89 package is found with

an IR temperature gun. Thermal simulation suggests a junction

temperature 10°C higher than the top of package temperature.

With additional ambient temperature and I/O power measure-

ments, θJA could be determined.

0.86mm

5.56mm

0.20mm

1.80mm

1.27mm

0.62mm

3.48mm

1.50mm

3.00mm

Figure 35. Recommended Land Pattern

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