ADIS16136SLASHPCBZ datasheet(4/20 Pages) AD

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ADIS16136

Data Sheet

Rev. A | Page 4 of 20

TIMING SPECIFICATIONS

TA = 25°C, VDD = 5 V, unless otherwise noted.

Table 2.

Normal Mode

Parameter

Description

Min1

Typ

Max

Unit

fSCLK

Serial clock

0.01

2.5

MHz

tSTALL

Stall period between data, see Figure 3

µs

tREADRATE

Read rate

µs

tCS

Chip select to clock edge

48.8

tDAV

DOUT valid after SCLK edge

tDSU

DIN setup time before SCLK rising edge

24.4

tDHD

DIN hold time after SCLK rising edge

48.8

tSCLKR, tSCLKF

SCLK rise and fall times

12.5

tDR, tDF

DOUT rise and fall times

12.5

tSFS

CS high after SCLK edge

Input sync positive pulse width

µs

Input sync to data ready output

300

µs

Input sync period

488

µs

Input sync low time

100

µs

Guaranteed by design and characterization but not tested in production.

Timing Diagrams

Figure 2. SPI Timing and Sequence

Figure 3. Stall Time and Data Rate

Figure 4. Input Clock Timing Diagram

SCLK

DOUT

DIN

R/W

MSB

DB14

LSB

DB13

DB12

DB10

DB11

DB2

LSB

DB1

tCS

tSFS

tDAV

tDHD

tDSU

SCLK

tREADRATE

tSTALL

SYNC

CLOCK (CLKIN)

DATA

READY

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