AD6657ABBCZRL datasheet(10/36 Pages) AD

10 / 36 page

AD6657A

Data Sheet

Rev. 0 | Page 10 of 36

TIMING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, fS = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless

otherwise noted.

Table 5.

Parameter

Description

Min

Typ

Max

Unit

SYNC TIMING REQUIREMENTS

See Figure 3 for details

tSSYNC

SYNC to rising edge of CLK setup time

0.24

tHSYNC

SYNC to rising edge of CLK hold time

0.40

SPI TIMING REQUIREMENTS

See Figure 60 for details, except where noted

tDS

Setup time between the data and the rising edge of SCLK

tDH

Hold time between the data and the rising edge of SCLK

tCLK

Period of the SCLK

Setup time between CSB and SCLK

Hold time between CSB and SCLK

tHIGH

SCLK pulse width high

tLOW

SCLK pulse width low

tEN_SDIO

Time required for the SDIO pin to switch from an input to

an output relative to the SCLK falling edge (not pictured in

Figure 60)

tDIS_SDIO

Time required for the SDIO pin to switch from an output to

an input relative to the SCLK rising edge (not pictured in

Figure 60)

Sync Input Timing Diagram

Figure 3. SYNC Input Timing Requirements

SYNC

CLK+

tHSYNC

tSSYNC

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