Data Sheet

AD6657A

Rev. 0 | Page 9 of 36

SWITCHING SPECIFICATIONS

otherwise noted.

Table 4.

Parameter

Temperature

Min

Typ

Max

Unit

CLOCK INPUT PARAMETERS

Input Clock Rate

Full

625

MHz

Conversion Rate1

Full

40

185

200

MSPS

CLK Pulse Width High (tCH)2

Full

2.7

ns

Aperture Delay (tA)2

Full

1.3

ns

Full

0.13

ps rms

DATA OUTPUT PARAMETERS

Data Propagation Delay (tPD)2

Full

3.0

4.0

4.9

ns

Full

3.1

4.0

4.9

ns

Full

−41

+6.1

+33

ns

Pipeline Delay (Latency)

Full

9

Cycles

With NSR Enabled

Full

12

Cycles

Wake-Up Time (from Standby)3

Full

0.5

µs

Wake-Up Time (from Power Down)3

Full

310

µs

OUT-OF-RANGE RECOVERY TIME

Full

2

Cycles

1

Conversion rate is the clock rate after the divider.

2

See Figure 2 for details.

3

Wake-up time is dependent on the value of the decoupling capacitors.

Data Output Timing Diagram

Figure 2. Data Output Timing (Timing for Channel C and Channel D Is Identical to Timing for Channel A and Channel B)

N – 1

N + 1

N + 2

N + 3

N + 4

N + 5

N

CLK+

CLK–

DCO+

DCO–

D10+AB (MSB)

D10–AB (MSB)

D0+AB (LSB)

D0–AB (LSB)

VIN

1/

D10A

D10B

D10A

D10B

D10A

D10B

D10A

D10B

D10A

D10B

D10A

D10B

D0A

D0B

D10A

D10B

D0A

D0B

D0A

D0B

D0A

D0B

D0A

D0B

D0A

D0B

D0A

D0B