CLC2058ISO8X datasheet(10/13 Pages) CADEKA

10 / 13 page

Data Sheet

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can be calculated as above with the desired signal ampli-

tudes using:

(VLOAD)RMS = VPEAK / √2

( ILOAD)RMS = ( VLOAD)RMS / Rloadeff

The dynamic power is focused primarily within the output

stage driving the load. This value can be calculated as:

PDYNAMIC = (VS+ - VLOAD)RMS × ( ILOAD)RMS

Assuming the load is referenced in the middle of the pow-

er rails or Vsupply/2.

Figure 4 shows the maximum safe power dissipation in

the package vs. the ambient temperature for the pack-

ages available.

0.5

1.5

-40

-20

Ambient Temperature (°C)

SOIC-8

Figure 4. Maximum Power Derating

Driving Capacitive Loads

Increased phase delay at the output due to capacitive

loading can cause ringing, peaking in the frequency re-

sponse, and possible unstable behavior. Use a series re-

sistance, RS, between the amplifier and the load to help

improve stability and settling performance. Refer to Fig-

ure 5.

Input

Output

Figure 5. Addition of RS for Driving

Capacitive Loads

Overdrive Recovery

An overdrive condition is defined as the point when ei-

ther one of the inputs or the output exceed their specified

voltage range. Overdrive recovery is the time needed for

the amplifier to return to its normal or linear operating

point. The recovery time varies, based on whether the

input or output is overdriven and by how much the range

is exceeded. The CLC2058 will typically recover in less

than 30ns from an overdrive condition. Figure 6 shows the

CLC2058 in an overdriven condition.

-20

-10

-5

Time (us)

Output

Input

VIN = 7.5Vpp

G = 5

Figure 6. Overdrive Recovery

Layout Considerations

General layout and supply bypassing play major roles

in high frequency performance. CaDeKa has evaluation

boards to use as a guide for high frequency layout and as

an aid in device testing and characterization. Follow the

steps below as a basis for high frequency layout:

• Include 6.8µF and 0.1µF ceramic capacitors for power

supply decoupling

• Place the 6.8µF capacitor within 0.75 inches of the power pin

• Place the 0.1µF capacitor within 0.1 inches of the power pin

• Remove the ground plane under and around the part,

especially near the input and output pins to reduce para-

sitic capacitance

• Minimize all trace lengths to reduce series inductances

Refer to the evaluation board layouts below for more in-

formation.

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