CLC1201 datasheet(13/15 Pages) CADEKA

13 / 15 page

Data Sheet

www.cadeka.com

Grounding

The output voltage of the CLC1201 is developed with

respect to the potential on the reference terminal (pin 8).

Simply tie the REF pin to the appropriate “local ground” to

resolve many grounding problems.

To isolate low level analog signals from a noisy digital

environment, many data-aquisistion components have

separate analog and digital ground pins. Use separate

ground lines (analog and digital) to minimize current flow

from sensitive areas to system ground. These ground

returns must be tied together at some point, usually best

at the ADC.

Layout Considerations

General layout and supply bypassing play major roles in

high frequency performance. CADEKA has evaluation

boards to use as a guide for high frequency layout and as

an aid in device testing and characterization. Follow the

steps below as a basis for high frequency layout:

▪ Include 6.8µF and 0.1µF ceramic capacitors for power

supply decoupling

▪ Placethe6.8µFcapacitorwithin0.75inchesofthepowerpin

▪ Placethe0.1µFcapacitorwithin0.1inchesofthepowerpin

▪ Remove the ground plane under and around the part,

especially near the input and output pins to reduce

parasitic capacitance

▪ Minimize all trace lengths to reduce series inductances

Refer to the evaluation board layouts below for more

information.

Evaluation Board Information

The following evaluation boards are available to aid in the

testing and layout of these devices:

Evaluation Board #

Products

CEB024

CLC1201 in SOIC-8

Evaluation Board Schematics

Evaluation board schematics and layouts are shown in

Figures 5-7. These evaluation boards are built for dual-

supply operation. Follow these steps to use the board in a

single-supply application:

1. Short -Vs to ground.

2. Use C3 and C4, if the -VS pin of the amplifier is not

directly connected to the ground plane.

Figure 5. CEB00x Schematic

Figure 6. CEB024 Top View

Figure 7. CEB024 Bottom View

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