CC2420-RTR1 datasheet(43/92 Pages) TI

43 / 92 page

CC2420

SWRS041B

Page 43 of 89

20 Radio control state machine

CC2420 has a built-in state machine that is

used

switch

between

different

operational states (modes). The change of

state is done either by using command

strobes or by internal events such as SFD

detected in receive mode.

The radio control state machine states are

shown in Figure 25. The numbers in

brackets refer to the state number

readable in the FSMSTATE status register.

Reading the FSMSTATE status register is

primarily for test / debug purposes.

Before using the radio in either RX or TX

mode, the voltage regulator and crystal

oscillator must be turned on and become

stable. The voltage regulator and crystal

oscillator start-up times are given in the

Electrical Specifications section on page

The crystal oscillator is controlled by

accessing the SXOSCON

/ SXOSCOFF

command strobes. The XOSC16M_STABLE

bit in the status register returned during

address transfer indicates whether the

oscillator is running and stable or not (see

Table 5). This status register can be polled

when waiting for the oscillator to start.

For

test

purposes,

the

frequency

synthesizer (FS) can also be manually

calibrated and started by using the

STXCAL

command strobe register. This

will not start a transmission before a

STXON

command strobe is issued. This is

not shown in Figure 25.

Enabling transmission is done by issuing a

STXON

or STXONCCA command strobe.

Turning off RF can be accomplished by

using one of the SRFOFF or SXOSCOFF

command strobe registers.

After reset the

CC2420 is in Power Down

mode. All configuration registers can then

be programmed in order to make the chip

ready to operate at the correct frequency

and mode. Due to the very fast start-up

time,

CC2420 can remain in Power Down

until a transmission session is requested.

As also described in the 4-wire Serial

Configuration and Data Interface section

on page 27, the crystal oscillator must be

running (IDLE) in order to have access to

the RAM and FIFOs.

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