DDR I/DDR II Phase Lock Loop Zero Delay Buffer

ICS9P935

REV H

12/1/08

ICS9P935

DDR I/DDR II Phase Lock Loop Zero Delay Buffer

4

Notes:

1.

Unused inputs must be held high or low to prevent them from floating.

2.

DC input signal voltage specifies the allowable DC execution of differential input.

3.

Differential inputs signal voltages specifies the differential voltage [VTR-VCP] required

for switching, where VTR is the true input level and VCP is the complementary input

level.

4.

at which the differential signal must be crossing.

Recommended Operating Condition (see note1)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Supply Voltage

1.7

1.8

1.9

V

Low level input voltage

CLK_INT, CLK_INC, FB_IN

V

High level input voltage

CLK_INT, CLK_INC, FB_IN

V

DC input signal voltage (note 2)

-0.3

V

DC input signal voltage swing

CLK_INT, CLK_INC

GND - 0.3

1.5

V

DC - CLK_INT, CLK_INC,

FB_IN

0.3

V

AC - CLK_INT, CLK_INC,

FB_IN

0.6

V

Output differential cross-voltage

(note 4)

V

Input differential cross-voltage

(note 4)

V

High level output current

-9

mA

Low level output current

9mA

High Impedance

Output Current

±10

mA

Operating free-air temperature

070

°C

Differential input signal voltage

(note 3)