HT16C24 datasheet(12/37 Pages) HOLTEK

12 / 37 page

HT16C24/HT16C24G

Rev. 1.20

September 23, 2011

A.C. Characteristics

VSS = 0V; VDD = 2.4 to 5.5V; Ta= -40 to +85°C

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

VDD

Condition

fLCD1

LCD Frame Frequency

1/4 duty, Ta =25°C

fLCD2

LCD Frame Frequency

1/4 duty, Ta =25°C

144

160

176

fLCD3

LCD Frame Frequency

1/4 duty,Ta=-40 to +85°C

124

fLCD4

LCD Frame Frequency

1/4 duty, Ta=-40 to +85°C

104

160

248

tOFF

VDD OFF Times

—

VDD drop down to 0V

—

tSR

VDD Slew Rate

—

0.05

—

V/ms

Note:

● If the conditions of Power on Reset timing are not satisfied during the power ON/OFF sequence, the internal

Power on Reset (POR) circuit will not operate normally.

● If the VDD voltage drops below the minimum voltage of operating voltage spec. during operating, the Power on

Reset timing conditions must also be satisfied. That is, the VDD voltage must drop to 0V and remain at 0V for

20ms (min.) before rising to the normal operating voltage.

A.C. Characteristics – I2C Interface

Symbol

Parameter

Condition

VDD=2.4V to 5.5V VDD=3.0V to 5.5V

Unit

Min.

Max.

Min.

Max.

fSCL

Clock frequency

—

100

—

400

KHZ

tBUF

bus free time

Time in which the bus

must be free before a new

transmission can start

4.7

—

1.3

—

μs

tHD: STA

Start condition hold time

After this period, the first

clock pulse is generated

—

0.6

—

μs

tLOW

SCL Low time

—

4.7

—

1.3

—

μs

tHIGH

SCL High time

—

0.6

—

μs

tSU: STA

Start condition setup time

Only relevant for repeated

START condition.

4.7

—

0.6

—

μs

tHD: DAT

Data hold time

—

tSU: DAT

Data setup time

—

250

—

100

—

SDA and SCL rise time

Note

—

0.3

μs

SDA and SCL fall time

Note

—

0.3

—

0.3

μs

tSU: STO

Stop condition set-up time

—

0.6

—

μs

tAA

Output Valid from Clock

—

3.5

—

0.9

μs

tSP

Input Filter Time Constant

(SDA and SCL Pins)

Noise suppression time

—

100

—

Note: These parameters are periodically sampled but not 100% tested.

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