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CC2500-RTR1 Folha de dados(PDF) 22 Page - Texas Instruments

Nome de Peças CC2500-RTR1
Descrição Electrónicos  Low-Cost Low-Power 2.4 GHz RF Transceiver
PDF  96 Pages
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Fabricante Electrônico  TI [Texas Instruments]
Página de início  http://www.ti.com
Logo TI - Texas Instruments

CC2500-RTR1 Folha de dados(HTML) 22 Page - Texas Instruments

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CC2500
SWRS040C
Page 22 of 89
Figure 7: Configuration Register Write and Read Operations
Parameter
Description
Min
Max
Units
SCLK
frequency
100 ns delay inserted between address byte and data byte (single access), or between
address and data, and between each data byte (burst access).
-
10
MHz
SCLK
frequency, single access
No delay between address and data byte
9
MHz
fSCLK
SCLK
frequency, burst access
No delay between address and data byte, or between data bytes
6.5
MHz
tsp,pd
CSn
low to positive edge on SCLK, in power-down mode
150
µs
tsp
CSn
low to positive edge on SCLK, in active mode
20
-
ns
tch
Clock high
50
-
ns
tcl
Clock low
50
-
ns
trise
Clock rise time
-
5
ns
tfall
Clock fall time
-
5
ns
Single access
55
-
ns
tsd
Setup data (negative SCLK edge) to
positive edge on SCLK
(tsd applies between address and data bytes, and
between data bytes)
Burst access
76
-
ns
thd
Hold data after positive edge on SCLK
20
-
ns
tns
Negative edge on SCLK to CSn high
20
-
ns
Table 16: SPI Interface Timing Requirements
Note: The minimum tsp,pd figure in Table 16 can be used in cases where the user does not read the
CHIP_RDYn
signal. CSn low to positive edge on SCLK when the chip is woken from power-down
depends on the start-up time of the crystal being used. The 150 us in Table 16 is the crystal oscillator
start-up time measured on CC2500EM reference design ([4]) using crystal AT-41CD2 from NDK.
10.1
Chip Status Byte
When the header byte, data byte or, command
strobe is sent on the SPI interface, the chip
status byte is sent by the
CC2500 on the SO
pin. The status byte contains key status
signals, useful for the MCU. The first bit, s7, is
the CHIP_RDYn signal; this signal must go low
before the first positive edge of SCLK. The
CHIP_RDYn
signal indicates that the crystal is
running.
Bits 6, 5, and 4 comprise the STATE value.
This value reflects the state of the chip. The
XOSC and power to the digital core is on in
the IDLE state, but all other modules are in
power down. The frequency and channel



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