R5F562TADDFM datasheet(69/94 Pages) RENESAS

69 / 94 page

R01DS0096EJ0100 Rev.1.00

Page 69 of 92

Apr 20, 2011

RX62T Group

5. Electrical Characteristics

5.3.3

Timing of On-Chip Peripheral Modules

Note: • tPcyc: PCLK cycle

Figure 5.8

SCK Clock Input Timing

Figure 5.9

SCI Input/Output Timing: Clock Synchronous Mode

Table 5.8

Timing of On-Chip Peripheral Modules (1)

Note:Items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3.

Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V

AVCC0 = AVCC = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC

Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V

AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC

Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V

AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC

Ta =

40 to +85C. Ta is the same under conditions 1 to 3.

Item

Symbol

Min.

Typ.

Max.

Unit

SCI

Input clock cycle

Asynchronous

tScyc

t

Pcyc

Figure 5.8

Clock synchronous

t

Pcyc

Input clock pulse width

tSCKW

0.4

t

Pcyc

0.6

t

Scyc

Input clock rise time

tSCKr

-20

Input clock fall time

tSCKf

-20

Output clock cycle

Asynchronous

tScyc

t

Pcyc

-ns

Clock synchronous

t

Pcyc

-ns

Output clock pulse width

tSCKW

0.4

t

Scyc

0.6

t

Scyc

Output clock rise time

tSCKr

-20

Output clock fall time

tSCKf

-20

Transmit data delay time (clock synchronous)

tTXD

Figure 5.9

Receive data setup time (clock synchronous)

tRXS

Receive data hold time (clock synchronous)

tRXH

tSCKW

tSCKr

tSCKf

tScyc

SCKn

(n = 0 to 2)

tTXD

tRXS tRXH

TxDn

RxDn

SCKn

n = 0 to 2

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