70592C datasheet(72/314 Pages) MICROCHIP

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PIC24HJXXXGPX06A/X08A/X10A

DS70592C-page 72

TABLE 6-3:

RESET DELAY TIMES FOR VARIOUS DEVICE RESETS

6.2.1

POR AND LONG OSCILLATOR

START-UP TIMES

The oscillator start-up circuitry and its associated delay

timers are not linked to the device Reset delays that

occur at power-up. Some crystal circuits (especially

low-frequency crystals) have a relatively long start-up

time. Therefore, one or more of the following conditions

is possible after the Reset signal is released:

• The oscillator circuit has not begun to oscillate

• The Oscillator Start-up Timer has not expired (if a

crystal oscillator is used)

• The PLL has not achieved a lock (if PLL is used)

The device will not begin to execute code until a valid

clock source has been released to the system. There-

fore, the oscillator and PLL start-up delays must be

considered when the Reset delay time must be known.

6.2.2

FAIL-SAFE CLOCK MONITOR

(FSCM) AND DEVICE RESETS

If the FSCM is enabled, it begins to monitor the system

clock source when the Reset signal is released. If a

valid clock source is not available at this time, the

device automatically switches to the FRC oscillator and

the user can switch to the desired crystal oscillator in

the Trap Service Routine.

6.2.2.1

FSCM Delay for Crystal and PLL

Clock Sources

When the system clock source is provided by a crystal

oscillator and/or the PLL, a small delay, TFSCM, is auto-

matically inserted after the POR and PWRT delay

times. The FSCM does not begin to monitor the system

clock source until this delay expires. The FSCM delay

time is nominally 500

μs and provides additional time

for the oscillator and/or PLL to stabilize. In most cases,

the FSCM delay prevents an oscillator failure trap at a

device Reset when the PWRT is disabled.

6.3

Special Function Register Reset

States

Most of the Special Function Registers (SFRs) associ-

ated with the CPU and peripherals are reset to a

particular value at a device Reset. The SFRs are

grouped by their peripheral or CPU function and their

Reset values are specified in each section of this

manual.

The Reset value for each SFR does not depend on the

type of Reset, with the exception of two registers. The

Reset value for the Reset Control register, RCON,

depends on the type of device Reset. The Reset value

for the Oscillator Control register, OSCCON, depends

on the type of Reset and the programmed values of the

oscillator Configuration bits in the FOSC Configuration

Reset Type

Clock Source

SYSRST Delay

System Clock

Delay

FSCM

Delay

See Notes

POR

EC, FRC, LPRC

TPOR + TSTARTUP + TRST

——

1, 2, 3

ECPLL, FRCPLL

TPOR + TSTARTUP + TRST

TLOCK

TFSCM

1, 2, 3, 5, 6

XT, HS, SOSC

TPOR + TSTARTUP + TRST

TOST

TFSCM

1, 2, 3, 4, 6

XTPLL, HSPLL

TPOR + TSTARTUP + TRST

TOST + TLOCK

TFSCM

1, 2, 3, 4, 5, 6

MCLR

Any Clock

TRST

——

WDT

Any Clock

TRST

——

Software

Any clock

TRST

——

Illegal Opcode

Any Clock

TRST

——

Uninitialized W

Any Clock

TRST

——

Trap Conflict

Any Clock

TRST

——

Note 1: TPOR = Power-on Reset delay (10

μs nominal).

2: TSTARTUP = Conditional POR delay of 20

μs nominal (if on-chip regulator is enabled) or 64 ms nominal

Power-up Timer delay (if regulator is disabled). TSTARTUP is also applied to all returns from powered-down

states, including waking from Sleep mode, only if the regulator is enabled.

3: TRST = Internal state Reset time (20

μs nominal).

4: TOST = Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods before releasing the

oscillator clock to the system.

5: TLOCK = PLL lock time (20

μs nominal).

6: TFSCM = Fail-Safe Clock Monitor delay (100

μs nominal).

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