MCP7940NT datasheet(8/36 Pages) MICROCHIP

8 / 36 page

MCP7940N

DS25010A-page 8

 2011 Microchip Technology Inc.

FIGURE 3-2:

ACKNOWLEDGE TIMING

3.1.2

DEVICE ADDRESSING AND OPERATION

A control byte is the first byte received following the

Start condition from the master device (Figure 3-2).

The control byte for accessing the SRAM and RTCC

registers are set to ‘1101111’. The RTCC registers and

the SRAM share the same address space.

The last bit of the control byte defines the operation to

be performed. When set to a ‘1’ a read operation is

selected, and when set to a ‘0’ a write operation is

selected. The next byte received defines the address of

the data byte (Figure 3-3). The upper address bits are

transferred first, followed by the Least Significant bits

(LSb).

Following the Start condition, the MCP7940N monitors

the SDA bus, checking the device type identifier being

transmitted. Upon receiving an ‘1101111’ code, the

slave device outputs an Acknowledge signal on the

SDA line. Depending on the state of the R/W bit, the

MCP7940N will select a read or write operation.

FIGURE 3-3:

ADDRESS SEQUENCE BIT ASSIGNMENTS

SCL

Transmitter must release the SDA line at this point

allowing the Receiver to pull the SDA line low to

acknowledge the previous eight bits of data.

Receiver must release the SDA line at this point

so the Transmitter can continue sending data.

Data from transmitter

SDA

Acknowledge

Bit

101

R/W

••

•

••

SRAM RTCC CONTROL BYTE

ADDRESS BYTE

CONTROL

CODE

111

X = Don’t Care

MCP7940NT Folha de dados(PDF) 8 Page - Microchip Technology

MCP7940NT Folha de dados(HTML) 8 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Folha de dados Download

Ligação URL