Rev. 1.00

�0

�a��� 0�� �011

Rev. 1.00

�1

�a��� 0�� �011

HT16K23

RAM Mapping 20*4/16*8 LCD Controller Driver with keyscan

communication between different ICs or modules. The two lines are a serial data line (SDA) and a

serial clock line (SCL). Both lines are connected to a positive supply via a pull-up resistor. When

the bus is free, both lines are high. The output stages of devices connected to the bus must have an

open-drain or open-collector output type to implement the required wired and function. Data transfer

is initiated only when the bus is not busy.

Data Validity

The data on the SDA line must be stable during the high period of the clock. The high or low state of

the data line can only change when the clock signal on the SCL line is Low (see as below).

SDA

SCL

Data line stable,

Data valid

Chang of data

allowed

START and STOP Conditions

● A high to low transition on the SDA line while SCL is high defines a START condition.

● A low to high transition on the SDA line while SCL is high defines a STOP condition.

● START and STOP conditions are always generated by the master. The bus is considered to be

busy after the START condition. The bus is considered to be free again a certain time after the

STOP condition.

● The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. In this

respect, the START(S) and repeated START (Sr) conditions are functionally identical.

P

S

SDA

SCL

SDA

SCL

START �ondition

STOP �ondition

Byte Format

Every byte put on the SDA line must be 8-bits long. The number of bytes that can be transmitted per

transfer is unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with

the most significant bit (MSB) first.

S

o�

S�

P

o�

S�

SDA

SCL

1

�

7

8

9

ACK

1

�

3-8

9

ACK

P

S�