LTC2208 datasheet(21/32 Pages) LINER

21 / 32 page

21521014p

LTC2152-14/

LTC2151-14/LTC2150-14

APPLICATIONS INFORMATION

the encode inputs directly. Otherwise, a transformer or

coupling capacitors are needed (Figures 9 and 10). The

maximum (peak) voltage of the input signal should never

exceed VDD +0.1V or go below –0.1V.

Clock Duty Cycle Stabilizer

For good performance the encode signal should have a

50% (±5%) duty cycle. If the optional clock duty cycle

stabilizer circuit is enabled, the encode duty cycle can

vary from 30% to 70% and the duty cycle stabilizer will

maintain a constant 50% internal duty cycle. If the encode

signal changes frequency or is turned off, the duty cycle

stabilizer circuit requires one hundred clock cycles to lock

onto the input clock. The duty cycle stabilizer is enabled

via SPI Register A2 (see SPI Control Register) or by CS

in parallel programming mode.

Figure 9. Sinusoidal Encode Drive

Forapplicationswherethesamplerateneedstobechanged

quickly, the clock duty cycle stabilizer can be disabled. If

the duty cycle stabilizer is disabled, care should be taken

to make the sampling clock have a 50% (±5%) duty cycle.

DIGITAL OUTPUTS

The digital outputs are double-data rate LVDS signals. Two

data bits are multiplexed and output on each differential

output pair. There are seven LVDS output pairs (D0_1+/

D0_1– through D12_13–/D12_13+). Overflow (OF+/OF–)

and the data output clock (CLKOUT+/CLKOUT–) each have

an LVDS output pair.

By default the outputs are standard LVDS levels: 3.5mA

output current and a 1.25V output common mode voltage.

LTC2152-14

VDD

21521014 F09

1.2V

10k

100

0.1µF

T1: MACOM ETC1-1-13

Figure 10. PECL or LVDS Encode Drive

VDD

LTC2152-14

PECL OR

LVDS INPUT

21521014 F10

1.2V

10k

100

0.1µF

ENC+

ENC–

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