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STV8162 Folha de dados(PDF) 9 Page - STMicroelectronics |
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STV8162 Folha de dados(HTML) 9 Page - STMicroelectronics |
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9 / 14 page ![]() Obsolete Product(s) - Obsolete Product(s) STV8162 Power dissipation and layout indications 9/14 5 Power dissipation and layout indications The power is mainly dissipated by the three device buffers. It can be calculated by the equation: P = (VIN1-VOUT1) x IOUT1 + (VIN2-VOUT2) x IOUT2 + (VIN3-VOUT3) x IOUT3 The following table lists the different RthJA values of these packages with or without a heat sink and the corresponding maximum power dissipation assuming: ● Maximum ambient temperature = 70° C ● Maximum junction temperature = 140° C Figure 8. Thermal resistance (junction-to-ambient) of DIP18 package without heatsink Figure 9. Metal plate mounted near STV8162D for heatsinking Table 5. Power dissipation Device Heat Sink RthJA in °C/W PMAX in W STV8162 No 50 1.4 Yes 15 4.6 STV8162D No 56 to 40 1.25 to 1.75 Yes 32 2.2 Copper area (cm²) (35 µm plus solder) Board is face-down To optimize the thermal conductivity of the copper layer and the exchanges with the air, the solder must cover the maximum amount of this area. 60 40 50 10 12 0 55 45 24 8 6 Test Board with “On Board” square heat sink area. Top View Bottom View |
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