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ADSP-21469KBZ-ENG2 Folha de dados(PDF) 23 Page - Analog Devices |
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ADSP-21469KBZ-ENG2 Folha de dados(HTML) 23 Page - Analog Devices |
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23 / 56 page  ADSP-21469/ADSP-21469W Preliminary Technical Data Rev. PrB | Page 23 of 56 | November 2008 Reset Running Reset The following timing specification applies to CLKOUT/ RESETOUT/RUNRSTIN pin when it is configured as RUNRSTIN. Table 15. Reset Parameter Min Max Unit Timing Requirements tWRST 1 RESET Pulse Width Low TBD TBD ns tSRST RESET Setup Before CLKIN Low TBD TBD ns 1 Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μσ while RESET is low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator). Figure 7. Reset CLKIN RESET tWRST tSRST Table 16. Running Reset Parameter Min Max Unit Timing Requirements tWRUNRST Running RESET Pulse Width Low TBD TBD ns tSRUNRST Running RESET Setup Before CLKIN High TBD TBD ns Figure 8. Running Reset CLKIN RUNRSTIN tWRUNRST tSRUNRST |
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